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1961 Commits

Author SHA1 Message Date
Chandler Klüser 8b0c5b78ee
Added QMTECH RP2040 Daughterboard 
Added new QMTECH Daughterboard with RP2040, which can be found in [AliExpress](https://www.aliexpress.com/item/1005005094654777.html).

Documentation can be found [here](https://github.com/ChinaQMTECH/DB_FPGA_with_RP2040)
 2023-09-01 04:47:09 -03:00
Florent Kermarrec b92c96b3a4 colorlight_i9plus: Cosmetic cleanups. 2023-08-30 17:22:11 +02:00
enjoy-digital 3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus 
[init] added colorlight i9+ based on XC7A50 FPGA
 2023-08-30 16:54:26 +02:00
Florent Kermarrec c960e85d11 targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs. 2023-08-30 09:59:23 +02:00
Florent Kermarrec 4bb064853d targets/efinix: Update RGMII PHYs (IOs are now directly excluded in PHYs). 2023-08-30 08:56:20 +02:00
Florent Kermarrec 347b477b07 sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. 
Now passing memtest with valid reported memory size:

       __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (d32a9529)

 LiteX git sha1: 85dadb82

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 48MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64.0KiB
SRAM:		6.0KiB
L2:		512B
SDRAM:		128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM:	128.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |01100000| delays: 01+-00
  m0, b03: |00000000| delays: -
  best: m0, b02 delays: 01+-00
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |01100000| delays: 01+-00
  m1, b03: |00000000| delays: -
  best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 11.7MiB/s
   Read speed: 17.4MiB/s
 2023-08-29 16:50:17 +02:00
enjoy-digital 4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd 
Allow use of OpenOCD for the Crosslink-NX
 2023-08-28 16:35:20 +02:00
enjoy-digital 6e7f58f2df
Merge pull request #524 from josuah/crosslink_nx_main_ram 
targets/lattice_crosslink_nx_evn: add main_ram section for firmware
 2023-08-28 16:34:34 +02:00
enjoy-digital 232e829b8f
Merge branch 'master' into crosslink_nx_main_ram 2023-08-28 16:34:27 +02:00
enjoy-digital a9ecbffe8f
Merge pull request #520 from josuah/crosslink_nx_prog_flash 
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
 2023-08-28 16:33:23 +02:00
enjoy-digital 387e361a55
Merge pull request #521 from josuah/crosslink_nx_spi_flash 
platforms/crosslink_nx_evn: add SPI flash support
 2023-08-28 16:33:02 +02:00
enjoy-digital 2c3d77b5be
Merge branch 'master' into crosslink_nx_spi_flash 2023-08-28 16:32:37 +02:00
enjoy-digital efb76133be
Merge pull request #519 from josuah/fix_crosslink_nx_uartbone 
Crosslink-NX EVN: fix UARTBone always disabled
 2023-08-28 16:31:29 +02:00
Florent Kermarrec 5799c35247 platforms/gsd_orangecrab: Set alt point to DFUProg. 2023-08-28 16:28:04 +02:00
Josuah Demangeon a5a6a313cc targets/lattice_crosslink_nx_evn: add main_ram section for firmware 
This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.

Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
 2023-08-18 19:56:58 +02:00
Icenowy Zheng ebfb9b8e01 sipeed_tang_mega_138k: new board 
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-08-15 16:33:13 +08:00
Josuah Demangeon 2e5c6eb7a7 platforms/crosslink_nx_evn: add SPI flash support 2023-08-11 16:46:52 +02:00
Josuah Demangeon 1a46bcce5e targets/lattice_crosslink_nx_evn: fix arguments in flash programming 2023-08-10 14:39:01 +02:00
Josuah Demangeon 3c0b6956cc platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone 
Also fix a warning about register_mem being deprecated, taking
inspiration from platforms/crosslink_nx_vip
 2023-08-09 18:07:13 +02:00
Josuah Demangeon 8172a304b3 platforms/crosslink_nx_evn: allow use of OpenOCD 2023-08-08 23:25:41 +02:00
enjoy-digital 3903cdee92
Merge pull request #517 from bayi/master 
Digilent CMOD A7 ISSIRAM fix
 2023-08-08 19:29:32 +02:00
enjoy-digital 9acc349893
Merge pull request #516 from josuah/crosslink_nx_uartbone 
platforms/crosslink_nx_evn: allow use of UARTBone
 2023-08-08 19:28:41 +02:00
Bayi 4362cb23a1
Fix Digilent Cmod A7 ISSIRAM reading 2023-08-05 19:56:32 +02:00
Bayi a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading 2023-08-05 19:56:15 +02:00
Josuah Demangeon 5412d0e0e9 platforms/crosslink_nx_evn: allow use of UARTBone 
This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.

This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
 2023-08-04 20:47:32 +02:00
Florent Kermarrec efc15a91a9 global: Use new WaitTimer integrated cast to int. 2023-08-01 14:56:35 +02:00
enjoy-digital f780b5faed
Merge pull request #513 from josuah/master 
lattice_ecp5_evn: add_jtagbone flag
 2023-08-01 11:38:23 +02:00
Josuah Demangeon 538399cb3b lattice_ecp5_evn: update OpenOCD syntax 
When running `litex_server`, this error appeared:

    can't read "_CHIPNAME": no such variable

This is a fix for the specific lattice_ecp5_evn board.
It also refreshes the OpenOCD syntax.
 2023-07-31 14:05:34 +02:00
Josuah Demangeon cbcf6df26f lattice_ecp5_evn: add_jtagbone flag 
This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
 2023-07-31 13:53:24 +02:00
Florent Kermarrec 2d3b81a532 efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it. 
See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD.
 2023-07-27 11:52:40 +02:00
Florent Kermarrec c1088befe5 targets/CRG: Add rst signal when missing. 
Allow properly reseting the PLL from the SoC.
 2023-07-26 16:56:27 +02:00
Florent Kermarrec ace789653f platforms/ti60_f225: Add connector numbering to ease review/schematic comparison. 2023-07-21 09:08:22 +02:00
Florent Kermarrec ce121663ff targets/uartbone: Update with LiteX change. 2023-07-20 15:42:47 +02:00
Florent Kermarrec 72a951081a xu8_pe3: Fix clk_p/n on pcie_x8. 2023-07-13 18:10:46 +02:00
Florent Kermarrec 18a3909a9c global: Switch to litex.gen.genlib.misc. 2023-07-06 22:11:45 +02:00
Florent Kermarrec 67be3ab677 targets: +x on alchitry_cu and vcu128. 2023-07-06 13:29:35 +02:00
enjoy-digital 34a1ced135
Merge pull request #510 from Mark1626/master 
alchitry_cu: add platform and target
 2023-07-06 09:08:24 +02:00
Mark1626 e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu 2023-06-27 21:35:55 +05:30
Mark1626 061a768495
Add Alchitry Cu board 2023-06-16 21:36:57 +05:30
Florent Kermarrec c49a50a934 platform/gsd_butterstick: Add mssing USB comment. 2023-06-16 09:10:47 +02:00
Florent Kermarrec 28ecb1e9f3 enclustra_mercury_xu8_pe3: Fix pcie_x8 and add GTH banks for pcie_x4/x8. 2023-06-15 17:57:38 +02:00
Florent Kermarrec 06e8829eb4 platforms/gsd_butterstick: Add default programmer to avoid breaking older designs. 2023-06-14 16:40:35 +02:00
Florent Kermarrec 58805f037c avnet_aesku40: Expose ethernet/etherbone parameters. 
To be able to test more easily usrgmii build.
 2023-06-13 09:26:07 +02:00
enjoy-digital e4343dcb86
Merge pull request #509 from iostat/patch-1 
Support SPI Flash in Colorlight 5A-75x
 2023-06-12 08:55:38 +02:00
Ilya Ostrovskiy 4705a0274e
Support SPI Flash in Colorlight 5A-75x 2023-06-09 13:43:34 -04:00
Florent Kermarrec 96175a9986 sitlinv_stlv7325_v2: Add default value to vccio. 2023-06-07 15:00:49 +02:00
enjoy-digital d874d344d2
Merge pull request #507 from hansfbaier/master 
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
 2023-06-07 14:08:14 +02:00
Hans Baier 765ee1a3ce sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V 2023-06-07 10:12:55 +07:00
Gabriel Somlo b01abce7d5 platform/stlv7325-v2: update VCCIO to fix --with-pcie generation 2023-06-01 16:45:33 -04:00
enjoy-digital 7fc8ca9816
Merge pull request #506 from sensille/rv901t-spiflash 
Add spiflash definition to linsn_rv901t board
 2023-05-30 22:36:14 +02:00