666ef9dad3
sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs
2021-11-29 11:46:32 +01:00
2fb734a0f2
sipeed_tang_nano*: adapt Gowin PLL changes in litex
2021-11-29 11:45:13 +01:00
b3175e4a9c
fairwares_xtrx: Generate Fallback/Operational bitstreams.
2021-11-26 16:20:44 +01:00
1829693877
fairwaves_xtrx: Integrate ICAP/SPIFlash (for update over PCIe).
2021-11-26 16:18:52 +01:00
2555fdff91
fairwaves_xtrx: Add SPIFlash, I2C, GPS, I2C, AUX, RF-Switches, RF-IC IOs.
2021-11-26 16:00:07 +01:00
fe14e16c1b
Merge branch 'master' into tang_primer
2021-11-23 19:04:09 +01:00
6954dd25eb
Set minimal core, since full does not work for some reason
2021-11-23 15:26:54 +01:00
b0dcd96964
added comments
2021-11-23 14:58:08 +01:00
0b7fabb864
FireAnt board support
2021-11-23 14:43:52 +01:00
2cc322e65d
Add initial support for Tang Primer board
2021-11-22 19:10:11 +01:00
70c0dbb185
targets/radiona_ulx3s: Remove SDRAM underflows debug pin.
2021-11-22 11:54:18 +01:00
b1817af8a8
Merge pull request #294 from antmicro/fix-ddr4-datacenter-platform
...
platforms: ddr4 datacenter: invert eth clocks
2021-11-21 19:11:13 +01:00
3e9e9bc425
platforms/sqrl_acorn: Add Multiboot Operational/Fallabck bistreams generation.
...
To allow recovery in case of PCIe update failure (Write error, power issue or crash).
2021-11-21 19:10:21 +01:00
60b769b624
efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine).
2021-11-16 18:53:15 +01:00
996f5b2edd
efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.
2021-11-16 18:12:42 +01:00
7ce6c4cf79
efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency).
2021-11-16 17:50:47 +01:00
99f4f97f00
efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target.
2021-11-16 17:41:26 +01:00
fa26b126df
platforms: ddr4 datacenter: invert eth clocks
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-11-16 12:55:50 +01:00
e16fa193fc
qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default
2021-11-15 10:23:01 +07:00
2272962315
qmtech_10cl001: fix wrong sdram clock pin
2021-11-15 09:54:17 +07:00
138dc1467e
quicklogic_quickfeather: Fix build with GPIOIn when cpu-type=None (IRQ not supported).
2021-11-14 09:30:52 +01:00
ed67b91fcc
quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3.
2021-11-14 09:26:29 +01:00
2d3422869c
quicklogic_quickfeather: Update clocking.
2021-11-14 09:19:19 +01:00
df468fcf85
quicklogic_quickfeather: Avoid add_csr calls (not required).
2021-11-14 08:54:49 +01:00
06bae58f48
efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working.
2021-11-12 19:43:28 +01:00
86f6d7e66b
efinix_trion_t120_bga576_dev_kit: Remove test command.
2021-11-12 18:06:11 +01:00
4e03f66fad
efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets.
...
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
2021-11-12 18:04:30 +01:00
77fffda9cd
efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :)
2021-11-12 16:41:42 +01:00
648d38da7e
quicklogic_quickfeather: add button and GPIOIn
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2021-11-12 13:21:00 +01:00
b6c5a85b98
Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.
...
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Nov 12 2021 08:37:48
BIOS CRC passed (2bec12a3)
Migen git sha1: 7507a2b
LiteX git sha1: f679992f
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
Read speed: 1.5MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-11-12 08:42:10 +01:00
d6fc4b412e
efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).
2021-11-12 07:58:51 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
855fd7e3d7
efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration...
2021-11-10 19:40:35 +01:00
224f527baa
efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration.
2021-11-10 12:07:30 +01:00
040e7b3104
quicklogic_quickfeather: Use initial EOS-S3 support/integration.
2021-11-09 18:59:37 +01:00
8ce83ce92f
efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working).
2021-11-09 16:13:40 +01:00
9a7e5f40b4
efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support.
...
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
2021-11-09 11:32:32 +01:00
ccebae6f55
targets/hyperram: Update integration.
2021-11-08 16:39:49 +01:00
184f41e61a
sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds).
...
Working correctly on hardware with updated CH552 firmware & patched litex_server...
2021-11-08 09:23:44 +01:00
8124c51dd0
Merge branch 'litex-hub:master' into master
2021-11-08 12:48:23 +07:00
d6bf2fd00e
terasic_sockit: Use standard SDRAM module from litedram
2021-11-08 12:48:03 +07:00
099d947a49
sqrl_acorn: fix vivado cfgbvs and config_voltage warnings
2021-11-07 16:18:22 +01:00
202b0e3e7d
sqrl_acorn: add option to use vivado programmer
2021-11-07 16:18:00 +01:00
f0356d8434
QMTech Daughterboard: remove xilinx specific attribute
2021-11-06 10:25:57 +07:00
a9847f15a7
qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz
2021-11-06 09:58:10 +07:00
b2813cfb70
use the right DRAM chip for the QMTech Altera boards
2021-11-06 08:45:03 +07:00
ee5638a96b
qmtech-boards: fix serial so that it gets replaced by daughterboard serial correctly
2021-11-06 06:49:25 +07:00
6e7c76b71e
fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe.
...
Fixes CI.
2021-11-05 15:22:55 +01:00
ceaaf67dfd
Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
2021-11-05 14:52:45 +01:00
01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes
...
10cl006: add missing spiflash option
2021-11-05 07:11:27 +01:00
3a25af1c28
10cl006: add missing spiflash option
2021-11-05 09:57:04 +07:00
0edce3a176
Add support for QMTech 5CEFA2 board (Cyclone V)
2021-11-05 09:53:25 +07:00
a482d7f6de
targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard.
2021-11-04 18:52:36 +01:00
9543b5efae
marble/marble_mini: Add berkeleylab prefix.
2021-11-04 18:42:16 +01:00
5e5ae880a4
targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel.
...
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
2021-11-04 16:36:25 +01:00
808befec3b
Merge pull request #283 from yetifrisstlama/master
...
add Marble-board platform and target file
2021-11-04 15:20:11 +01:00
a4f8f12067
Merge pull request #284 from hansfbaier/master
...
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-04 15:18:16 +01:00
d950b3feb5
Use built-int RS232 port
...
Signed-off-by: lapd <lapd@soc.one>
2021-11-03 22:50:40 +07:00
7aa639ac0f
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-02 09:34:25 +07:00
e645eb243b
add marble board platform and target file
2021-10-28 18:41:22 +02:00
0c3f5b0fe1
prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).
2021-10-27 17:27:07 +02:00
207afb98fc
ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX).
2021-10-27 16:29:46 +02:00
91818bc5f0
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
2021-10-26 17:01:55 +02:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
...
Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
f230eaf9bc
efinix_trion_t120_bga576: Add Tristate test code.
2021-10-25 15:01:34 +02:00
0ac0f9e75d
efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream.
2021-10-25 12:49:48 +02:00
fc05379929
efinix_xyloni_dev_kit: Use PLL.
2021-10-25 12:16:47 +02:00
16a629269d
efinix_xyloni_dev_kit: Describe IOs in similar order than the other platforms.
2021-10-22 14:52:38 +02:00
394ea23b99
efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.
2021-10-22 14:47:12 +02:00
75fd276dbe
efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k.
2021-10-21 11:34:55 +02:00
dc1328f1a5
efinix_xyloni_dev_kit: Fix copyrights.
2021-10-21 10:12:46 +02:00
012c1d9705
efinix_trion_t20: Minor changes (move serial to platform, fix platform copyright).
2021-10-21 10:10:35 +02:00
0cf9793be5
Merge pull request #282 from AndrewD/master
...
efinix: xyloni dev board basic support
2021-10-21 10:06:25 +02:00
7525132907
litex_acorn_baseboard/video: Switch to 800x600@60Hz.
2021-10-19 16:34:28 +02:00
c548b1c1e2
efinix: xyloni dev board basic support
...
* This works: efinix_xyloni_dev_kit.py --cpu-type None --build --load --flash
* issues with SPIflash - wrong generation for tristates miso mosi for
some reason
2021-10-19 11:23:29 +11:00
a53f17380f
Merge pull request #271 from antmicro/add-data-center-board
...
WIP: boards: added datacenter DDR4 RDIMM tester board
2021-10-18 13:36:37 +02:00
a2261a1e9a
Merge pull request #280 from developandplay/master
...
Fix tang nano loopback and button
2021-10-16 09:09:39 +02:00
9645a9a310
efinix_trion_xx: append device with timing model
2021-10-16 07:36:06 +02:00
a3c7446a2b
Fix tang nano loopback and button
2021-10-16 04:35:23 +02:00
a4d330dd2c
Merge pull request #279 from mmicko/efinix_t20_flash
...
Enable writing to flash for T20
2021-10-15 18:38:08 +02:00
3730d96709
litex_acorn_baseboard: Add SPIFlash support.
2021-10-15 18:22:08 +02:00
bdf2848208
platforms/digilent_arty: Avoid commas in spiflash4x.
2021-10-15 18:22:06 +02:00
1f65d37121
Enable writing to flash for T20
2021-10-15 16:44:35 +02:00
d9638c40b8
Initial support for Efinix Trion T20 BGA256 Dev Kit
2021-10-15 12:26:15 +02:00
914e330a86
efinix_trion_t120_bga576_dev_kit: Add Flash support (Through openFPGALoader).
2021-10-15 09:38:43 +02:00
195bf176cf
efinix_trion_t120_bga576: Add SPIFlash support (X1 for now).
2021-10-14 19:16:01 +02:00
03c34e31cd
efinix_trion_t120_bga576: Add PLL to CRG and increase default sys_clk to 100MHz.
2021-10-14 15:45:26 +02:00
414b3fa636
efinix_trion_t120_bga576: Add Ethernet pins of the 2 RGMII PHYs.
2021-10-14 11:51:17 +02:00
2ea803b7d1
efinix_trion_t120_bga576: Set no_we on integrated_main_ram.
...
To allow --integrated-main-ram-size use.
2021-10-14 10:19:18 +02:00
430918756d
efinix_trion_t120_bga576: Add PMODs connectors and use USB-UART/PMOD_E as Serial.
2021-10-14 10:10:42 +02:00
36897f4646
efinix_trion_t120_bga576: Disable Identifier (crashes design) and move no_we, working.
...
./efinix_trion_t120_bga576_dev_kit.py --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (b23a7321)
Migen git sha1: 7507a2b
LiteX git sha1: 8316fbf1
--=============== SoC ==================--
CPU: VexRiscv @ 40MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-10-14 09:39:54 +02:00
9145ff97d2
efinix_trio_t120_bga576: Add Switches pins.
2021-10-14 09:29:12 +02:00
ad773b6f2f
efinix_trion_t120_bga576: Fix argparse description.
2021-10-13 17:28:43 +02:00
6c17d76a92
targets/efinix_trion_t120_bga576: Switch to SoCCore (with CPU) and use button as reset (and AsyncResetSynchronizer).
2021-10-13 16:35:14 +02:00
5b4558c9b9
platforms/efinix_trion_t120_bga576: Add Buttons and Serial (other PMOD USB-UART).
2021-10-13 16:32:58 +02:00
a4d178a740
Add Efinix Trio T120 BGA576 Dev-Kit initial support (LedChaser).
2021-10-13 12:29:53 +02:00
83e64fbd64
targets/qmtech_10cl006: +x.
2021-10-13 12:16:41 +02:00
e29bcd30a6
litex_acorn_baseboard: Add some M2 signals and set devslp to 0.
2021-10-12 11:54:17 +02:00
Ilia Sergachev
Florent Kermarrec
Miodrag Milanovic
Alessandro Comodi
Hans Baier
Gwenhael Goavec-Merou
Ilia Sergachev
lapd
Michael Betz
Andrew Dennison
Martin Troiber