Sebastien Bourdeauducq
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04f29e97e2
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soc: remove unnecessary imports
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2015-04-01 15:15:09 +08:00 |
|
Sebastien Bourdeauducq
|
5113301130
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soc: improve memory region conflict check
|
2015-04-01 15:14:02 +08:00 |
|
Sebastien Bourdeauducq
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980791e2b8
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soc: remove ns function
|
2015-04-01 14:33:12 +08:00 |
Florent Kermarrec
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b313772a0c
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sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
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2015-03-29 12:34:40 +02:00 |
|
Florent Kermarrec
|
be20fbabe4
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soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
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2015-03-28 23:35:44 +01:00 |
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Florent Kermarrec
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0649ded5fd
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soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
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2015-03-28 23:10:33 +01:00 |
|
Florent Kermarrec
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a8d91c0c1d
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sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
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2015-03-28 16:35:15 +01:00 |
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Florent Kermarrec
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75ee8a5db9
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sdram/phy/simphy: OK with DDR3
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2015-03-28 01:59:55 +01:00 |
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Florent Kermarrec
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51ce7cad6f
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sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
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2015-03-28 01:18:35 +01:00 |
|
Florent Kermarrec
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a95b3f8f13
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sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
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2015-03-28 01:17:50 +01:00 |
|
Florent Kermarrec
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7fe748e1b0
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sdram/module: clean up tREFI. (use 64ms/8k or 4k)
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2015-03-28 01:09:21 +01:00 |
|
Florent Kermarrec
|
9137b91e9e
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sdram: remove nbits from modules and databits from GeomSettings
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2015-03-26 23:27:37 +01:00 |
|
Florent Kermarrec
|
9a9af17aca
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sdram/phy/simphy: remove use of iter
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2015-03-26 23:02:23 +01:00 |
|
Florent Kermarrec
|
e6de4b1bf9
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sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
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2015-03-26 22:28:32 +01:00 |
|
Florent Kermarrec
|
257706517e
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software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
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2015-03-26 00:01:42 +01:00 |
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Florent Kermarrec
|
ff11cb97a9
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sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
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2015-03-25 17:22:26 +01:00 |
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Florent Kermarrec
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ba8b24df57
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sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
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2015-03-25 16:57:38 +01:00 |
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Florent Kermarrec
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7ea9e2ba89
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sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
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2015-03-25 16:56:29 +01:00 |
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Florent Kermarrec
|
20207c9c32
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liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
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2015-03-22 11:11:37 +01:00 |
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Florent Kermarrec
|
c77562f44b
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liteusb: make oe_n optional on ft2232h phy
|
2015-03-22 10:56:56 +01:00 |
|
Florent Kermarrec
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ed5746a1fe
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liteusb: fix imports
|
2015-03-22 10:56:29 +01:00 |
|
Florent Kermarrec
|
92f81409f2
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sdram/module: fix tREFI on AS4C16M16
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2015-03-22 03:20:02 +01:00 |
|
Florent Kermarrec
|
30c2521eb0
|
sdram: pass sdram_controller_settings to SDRAMSoC
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2015-03-21 23:12:18 +01:00 |
|
Florent Kermarrec
|
70469e1f37
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sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
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2015-03-21 21:32:39 +01:00 |
|
Florent Kermarrec
|
9bc71f374a
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rename sdram mapping to main_ram
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2015-03-21 21:01:46 +01:00 |
|
Florent Kermarrec
|
c55199deb9
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misoclib/soc: add _integrated_ to cpu options to avoid confusion
|
2015-03-21 20:51:37 +01:00 |
|
Florent Kermarrec
|
c60d99583d
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sdram/module: add tREFI uniformization to TODO
|
2015-03-21 18:59:16 +01:00 |
|
Florent Kermarrec
|
0f9b0c6f0f
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sdram/module: add MT47H128M8 DDR2 (used for a customer)
|
2015-03-21 18:52:10 +01:00 |
|
Florent Kermarrec
|
45eb5090db
|
sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
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2015-03-21 18:41:59 +01:00 |
|
Florent Kermarrec
|
a560ba35bd
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sdram/module: add AS4C16M16 for minispartan6
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2015-03-21 18:38:53 +01:00 |
|
Florent Kermarrec
|
854058a8db
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sdram/module: add description and TODO list
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2015-03-21 17:44:04 +01:00 |
|
Florent Kermarrec
|
52924ee1f2
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sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
|
2015-03-21 17:25:36 +01:00 |
|
Florent Kermarrec
|
fd2f8d4bb4
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sdram: define MT46V32M16 and use it on m1/mixxeo
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2015-03-21 17:04:58 +01:00 |
|
Florent Kermarrec
|
de2f1c31d5
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sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
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2015-03-21 16:56:53 +01:00 |
|
Florent Kermarrec
|
6e4b7c6cfd
|
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
|
2015-03-21 12:55:39 +01:00 |
|
Florent Kermarrec
|
9107710f03
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litexxx cores: use default baudrate of 115200 for all tests
|
2015-03-20 12:22:53 +01:00 |
|
Florent Kermarrec
|
82fe83a1c4
|
sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now)
|
2015-03-19 16:08:03 +01:00 |
|
Florent Kermarrec
|
84b631c929
|
liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
|
2015-03-19 14:52:02 +01:00 |
|
Florent Kermarrec
|
6bdf60567c
|
liteeth/mac/core: fix hw_preamble_crc register generation
|
2015-03-19 13:03:27 +01:00 |
|
Florent Kermarrec
|
236ea0f572
|
liteeth: use bios ip_address in example designs
|
2015-03-18 18:18:43 +01:00 |
|
Florent Kermarrec
|
70f1f96fda
|
litescope/drivers: do not build regs when addrmap is None
|
2015-03-17 16:04:31 +01:00 |
|
Florent Kermarrec
|
a266deb58e
|
LiteXXX cores: fix frequency print in test/test_regs.py
|
2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
|
d2cb41bc63
|
LiteXXX cores: convert port parameter to int if is digit in test/make.py
|
2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
|
2327710387
|
liteeth/phy/gmii : set tx_er to 0 only if it exits
|
2015-03-17 12:24:06 +01:00 |
|
Florent Kermarrec
|
408d0fd2dd
|
liteeth: use default programmer in make.py
|
2015-03-17 12:12:21 +01:00 |
|
Florent Kermarrec
|
ec6ae75065
|
liteeth: use CRG from Migen in base example
|
2015-03-17 12:11:51 +01:00 |
|
Florent Kermarrec
|
a874f85854
|
litescope: use CRG from Migen
|
2015-03-17 11:52:54 +01:00 |
|
Florent Kermarrec
|
faf185d58d
|
liteeth: make gmii phy generic
|
2015-03-16 23:04:37 +01:00 |
|
Florent Kermarrec
|
d8b59c03a2
|
litesata: avoid hack on kc705 platform with new mibuild toolchain management
|
2015-03-14 01:08:36 +01:00 |
|
Florent Kermarrec
|
28d04ec300
|
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
|
2015-03-14 00:49:19 +01:00 |