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906 commits 42 branches 14 tags 31 MiB
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129 commits

Author SHA1 Message Date
Robert Jordens
0836f2814a bus/csr: new simulation api 2014-03-19 18:12:27 -07:00
Sebastien Bourdeauducq
90f0dfad63 Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator 2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq
63c1d7e4b7 New simulation API 2014-01-26 22:19:43 +01:00
Sebastien Bourdeauducq
29f7b94e37 bus/wishbone/sram: expose memory component 2013-11-24 23:43:14 +01:00
Sebastien Bourdeauducq
c5342c5b5c bus/wishbone: style 2013-11-24 23:42:54 +01:00
Sebastien Bourdeauducq
948d7e7332 lasmibus/Crossbar: more flexible master assignment 2013-11-23 17:51:22 +01:00
Sebastien Bourdeauducq
99c53ed9e8 Better record layout parameterization mechanism 2013-10-23 12:54:50 +02:00
Sebastien Bourdeauducq
dac10f5570 bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules 2013-08-26 20:33:34 +02:00
Sebastien Bourdeauducq
2cf6b6c768 wishbone/SRAM: fix non-32-bit bus 2013-08-26 20:32:59 +02:00
Florent Kermarrec
33ca4d778f wishbone2lasmi: configurable data width 2013-08-26 20:29:12 +02:00
Florent Kermarrec
628fa8ce9e wishbone : add DownConverter 2013-08-26 20:28:09 +02:00
Florent Kermarrec
a653a6144b wishbone2lasmi : add support for 32 bits lasmim data width 2013-08-20 18:49:46 +02:00
Sebastien Bourdeauducq
246b860a85 csr: new data width API 2013-07-28 16:33:36 +02:00
Sebastien Bourdeauducq
6ba0d4bd0d bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
Sebastien Bourdeauducq
f62eff0309 bus/csr/Initiator: correct read latency 2013-07-27 15:37:47 +02:00
Robert Jördens
fe18397acc wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect) 2013-07-22 10:30:44 +02:00
Sebastien Bourdeauducq
5b36f688ea Remove ASMI 2013-07-16 18:50:50 +02:00
Sebastien Bourdeauducq
b016a60b85 lasmibus: fix master locking 2013-07-15 21:45:07 +02:00
Florent Kermarrec
f5ddd33e7e dfi: split phase description 2013-07-10 19:56:47 +02:00
Sebastien Bourdeauducq
43fe16ef73 bus/lasmibus: add separate req/data ack to target and initiator 2013-07-10 19:09:51 +02:00
Sebastien Bourdeauducq
7e6fbd31a4 lasmibus/crossbar: simplify master ack generation 2013-07-07 18:56:43 +02:00
Sebastien Bourdeauducq
d0caa738bd FSM: new API 2013-06-25 22:17:39 +02:00
Sebastien Bourdeauducq
d6f7b4cee6 lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete) 2013-06-17 23:36:03 +02:00
Sebastien Bourdeauducq
6d6d232cad lasmibus/crossbar: better switching policy 2013-06-15 16:51:09 +02:00
Sebastien Bourdeauducq
ac2cde0e87 asmibus: remove port sharing 2013-06-14 18:34:36 +02:00
Sebastien Bourdeauducq
0c52c08989 bus/asmibus: fix slot aging timer 2013-06-14 17:57:43 +02:00
Sebastien Bourdeauducq
1ec1fb9ebe bus/lasmibus/Crossbar: support cba_shift=0 2013-06-11 18:15:49 +02:00
Sebastien Bourdeauducq
fe54c68762 lasmi: fix minor problems 2013-06-10 22:49:33 +02:00
Sebastien Bourdeauducq
932bfa7e75 bus: Wishbone -> LASMI bridge (untested) 2013-06-10 18:52:07 +02:00
Sebastien Bourdeauducq
f2e2397c9d bus/lasmibus: bugfixes 2013-06-09 23:36:32 +02:00
Sebastien Bourdeauducq
a836cba790 bus/lasmibus: add target and initiator 2013-06-09 16:03:22 +02:00
Sebastien Bourdeauducq
35f9f2e9d7 bus/lasmi: interface definition and crossbar (untested) 2013-06-08 15:49:50 +02:00
Kenneth Ryerson
85813b3b58 csr/sram: fix reads on high addresses when word_bits != 0 2013-06-03 21:52:23 +02:00
Kenneth Ryerson
e5e3492afe csr/sram: fix page_bits computation 2013-06-03 21:51:44 +02:00
Sebastien Bourdeauducq
ebbd5ebcd2 bus/csr/SRAM: better handling of writes to memories larger than the CSR width 2013-05-30 18:45:04 +02:00
Sebastien Bourdeauducq
bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq
70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
5208baada8 bus/wishbone/SRAM: support init and read_only 2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq
7ada0159fd bus/csr/SRAM: support init 2013-05-19 20:53:37 +02:00
Sebastien Bourdeauducq
792b8fed1b bus/asmi: port sharing support 2013-05-12 15:58:39 +02:00
Sebastien Bourdeauducq
8e11fcf1d0 bus/csr/SRAM: fix Module conversion errors 2013-04-14 13:55:04 +02:00
Sebastien Bourdeauducq
29b468529f bus: replace simple bus module with new bidirectional Record 2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq
c4f4143591 New CSR API 2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq
51bec340ab sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq
04df076fba bank: automatic register naming 2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
80970b203c bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq
174e8cb8d6 bus/asmibus: use fhdl.module API 2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq
2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq
b75fb7f97c csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
Sebastien Bourdeauducq
9b4ca987e0 bus/csr: support memories with larger word width than the bus (read only) 2013-03-03 19:27:13 +01:00