Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
1293 commits 42 branches 14 tags 31 MiB
Commit graph

290 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
1d1189506a mibuild: support multiple specifications of include file and sources 2015-04-04 18:58:02 +08:00
Yann Sionneau
ce429841d5 kc705: fix typo in platform file (LPC definition) 2015-04-02 20:21:20 +08:00
Sebastien Bourdeauducq
c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 
This reverts commit f03aa76292.
 2015-03-30 19:41:16 +08:00
Florent Kermarrec
15e24b6c10 mibuild/platforms: fix minispartan6 2015-03-30 11:42:14 +02:00
Florent Kermarrec
f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Sebastien Bourdeauducq
21c5fb6f6c Merge branch 'master' of github.com:m-labs/migen 2015-03-30 00:52:15 +08:00
Sebastien Bourdeauducq
19a6157478 platforms/lx9_microboard,usrp_b100: fix bitgen opts 2015-03-30 00:44:56 +08:00
Florent Kermarrec
263fc47728 platforms/kc705: fix .bin generation with ISE and Vivado 2015-03-29 21:15:20 +08:00
Florent Kermarrec
17f3590a7c platforms/kc705: add iMPACT programmer 2015-03-29 12:15:39 +02:00
Florent Kermarrec
ec080479da mibuild/sim: use the same architecture we use for others backends 2015-03-27 14:14:49 +01:00
Florent Kermarrec
de31103cce platforms/minispartan6: add ftdi_fifo pins 2015-03-22 11:20:22 +01:00
Florent Kermarrec
200979fb81 platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz 2015-03-22 03:37:27 +01:00
Florent Kermarrec
7440ccd65b mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working) 2015-03-21 20:27:11 +01:00
Florent Kermarrec
1d2e7e8390 mibuild/platforms/minispartan6: adapt to recent changes (able to build simple example) 2015-03-21 18:31:50 +01:00
Florent Kermarrec
78b4f313bf mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25) 2015-03-21 18:28:09 +01:00
Florent Kermarrec
1a03c340c9 mibuild/platforms: review and fix small mistakes 2015-03-21 18:23:35 +01:00
Florent Kermarrec
3a38626556 mibuild/platforms: add minispartan6 (from Matt O'Gorman) 2015-03-21 18:22:26 +01:00
Robert Jordens
4fe888702d pipistrello: switch is a button 2015-03-19 18:56:49 +01:00
Robert Jordens
47ea451315 pipistrello: compress and load bitstream at 6MHz 2015-03-19 18:48:45 +01:00
Robert Jordens
860b72c8b6 pipistrello: rename sdram->ddram 2015-03-19 18:48:22 +01:00
Florent Kermarrec
3aee58f484 mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented) 2015-03-18 18:54:22 +01:00
Florent Kermarrec
ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec
500e58ce7d mibuild/platform/versa: fix clock_constraints 2015-03-17 15:25:10 +01:00
Florent Kermarrec
e07b7f632c mibuild/lattice: use ODDRXD1 and new synthesis directive 2015-03-17 14:59:36 +01:00
Florent Kermarrec
022ac26c22 mibuild/lattice: add LatticeAsyncResetSynchronizer 2015-03-17 12:42:36 +01:00
Florent Kermarrec
c06ab82f13 mibuild/platforms/versa: add ethernet clock constraints 2015-03-17 12:04:00 +01:00
Florent Kermarrec
ba2aeb08be mibuild/platforms/versa: add rst_n 2015-03-17 11:51:34 +01:00
Florent Kermarrec
6dd8d89c6c mibuild/lattice: fix LatticeDDROutput 2015-03-17 09:40:25 +01:00
Florent Kermarrec
9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code 
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
 2015-03-17 00:40:26 +01:00
Florent Kermarrec
b5a9909b08 mibuild/xilinx/common: add LatticeDDROutput 2015-03-16 22:57:18 +01:00
Florent Kermarrec
993059a59c mibuild/xilinx/common: add XilinxDDROutput 2015-03-16 22:53:05 +01:00
Florent Kermarrec
b3b1209c62 mibuild/platforms: add ethernet to versa 2015-03-16 22:24:10 +01:00
Florent Kermarrec
fab0b0b161 mibuild/platforms: add user_dip_btn to versa 2015-03-16 22:11:15 +01:00
Florent Kermarrec
d6041879dd mibuild/lattice: use new Toolchain/Platform architecture 2015-03-16 21:24:21 +01:00
Florent Kermarrec
e903b62af1 mibuild/altera: use new Toolchain/Platform architecture 2015-03-16 21:07:55 +01:00
Florent Kermarrec
f7bfa13144 mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton) 2015-03-16 19:02:34 +01:00
Sebastien Bourdeauducq
aef9275c99 mibuild/xilinx: export special_overrides dictionary 2015-03-14 10:45:11 +01:00
Sebastien Bourdeauducq
d34b7d7a6b mibuild/xilinx: remove obsolete CRG_DS 2015-03-14 00:27:24 +01:00
Sebastien Bourdeauducq
6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Sebastien Bourdeauducq
702d177c85 mibuild: get rid of Platform factory function, cleanup 2015-03-13 23:25:15 +01:00
Florent Kermarrec
ff266bc2ee migen/genlib/io: add DifferentialOutput and Xilinx implementation 2015-03-12 19:30:57 +01:00
Florent Kermarrec
c8ba8cde8e migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild 2015-03-12 18:38:53 +01:00
Florent Kermarrec
00e8616de2 mibuild/sim: clean up (thanks sb) 2015-03-10 16:41:52 +01:00
Sebastien Bourdeauducq
555c444da2 mibuild/sim/dut_tb: fix permissions 2015-03-10 11:06:55 +01:00
Florent Kermarrec
9d8f1cd61d mibuild/sim: get serial dev from /tmp/simserial 2015-03-10 00:42:54 +01:00
Florent Kermarrec
70a3e8081c mibuild/sim: add support for pty 2015-03-09 23:31:11 +01:00
Florent Kermarrec
aa609bee15 mibuild/sim: remove hack, the issue was in gateware (padding) 2015-03-09 20:57:20 +01:00
Florent Kermarrec
efc5f221d9 mibuild/sim: clean up and move eth struct to sim 2015-03-09 14:40:33 +01:00
Florent Kermarrec
a72c091bc2 mibuild/sim: regroup console_tb/ethernet_tb in dut_tb 2015-03-09 14:40:31 +01:00
Florent Kermarrec
e82b540a96 mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up 2015-03-09 13:30:21 +01:00
Robert Jordens
3e84c66ba9 vivado: permit resources without pins 
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
 2015-03-09 13:30:19 +01:00
Florent Kermarrec
e60a97534b mibuild/sim: able to visualize arp requests with wireshark 
now need to find why that is not responding...
 2015-03-06 20:16:30 +01:00
Florent Kermarrec
a64acdfa65 mibuild/sim: able to send ethernet frame from sim to server.py 2015-03-06 12:49:56 +01:00
Florent Kermarrec
0029b87628 mibuild/sim: add ethernet pins to verilor.py 2015-03-06 12:20:17 +01:00
Florent Kermarrec
658d4d4c49 platforms/sim: add ethernet pins 2015-03-06 10:20:26 +01:00
Florent Kermarrec
3d7f9fd685 mibuild/sim/server_tb: use SERIAL_SINK_ACK 2015-03-04 00:55:35 +01:00
Florent Kermarrec
2d6fbd7902 mibuild/sim: use /tmp/simsocket sockaddr for server 2015-03-03 22:52:28 +01:00
Florent Kermarrec
f4b060f6fe mibuild/sim: avoid updating end at each cycle (simulation speedup) 2015-03-03 18:01:14 +01:00
Florent Kermarrec
5ec26a49c3 mibuild/sim: simplify console_tb with sim struct 2015-03-03 17:57:58 +01:00
Florent Kermarrec
991572f4fe mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm) 
Using a server allow us to create a virtual UART (and ethernet TAP in the future).

1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation

This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping  ethernet for ARTIQ in simulation.
 2015-03-03 17:38:22 +01:00
Sebastien Bourdeauducq
f154c2e7ec xilinx/programmer/vivado: fix Linux support 2015-03-03 02:06:39 +00:00
Sebastien Bourdeauducq
154ad54a8e platforms/kc705: fix imports 2015-03-03 02:03:14 +00:00
Florent Kermarrec
a56fce045b Merge branch 'master' of http://github.com/m-labs/migen 2015-03-02 23:24:48 +01:00
Florent Kermarrec
29c5bb8bcd mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default) 2015-03-02 23:23:23 +01:00
Sebastien Bourdeauducq
36f4b68dd8 mibuild/sim: style fixes 2015-03-02 21:56:20 +00:00
Florent Kermarrec
382ca374c3 mibuild: initial Verilator support 2015-03-01 18:27:46 +01:00
Sebastien Bourdeauducq
961b4bfb4c platforms/pipistrello: remove unconnected SDRAM pins 2015-02-28 16:20:44 -07:00
Robert Jordens
03431ece9f pipistrello: fix ddram dqs, cleanup constraints, add pullup/downs 2015-02-28 16:16:47 -07:00
Robert Jordens
75290aa0f3 pipistrello: switch back to xc3sprog and fast (papilio) speed 2015-02-28 16:16:47 -07:00
Florent Kermarrec
eb8ba145de kx705: add programmer parameter 2015-02-28 23:34:57 +01:00
Florent Kermarrec
b53e2b0d6e fix xilinx/programmer with Vivado 2015-02-28 19:33:20 +01:00
Florent Kermarrec
87d8ff2de7 xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine) 2015-02-28 03:38:47 +01:00
Florent Kermarrec
54a8a52e90 xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...)) 2015-02-27 09:05:23 +01:00
Robert Jordens
2b0937153d xilinx/programmer: fix xc3sprog (GenericProgrammer) 2015-02-26 21:36:15 -07:00
Robert Jordens
8de5b947bd pipistrello: use fpgaprog 2015-02-26 21:34:02 -07:00
Robert Jordens
ca52aa5b8c add fpgaprog programmer 2015-02-26 21:33:49 -07:00
Robert Jordens
5b5d2d15b8 add pipistrello platform 2015-02-26 21:33:42 -07:00
Sebastien Bourdeauducq
ba26a400e3 Merge branch 'master' of https://github.com/m-labs/migen 2015-02-26 21:32:39 -07:00
Sebastien Bourdeauducq
28c219ebd2 platforms/kc705: add user SMA clock 2015-02-26 16:22:22 -07:00
Yann Sionneau
dbdb263acc mibuild/kc705: add missing pins on FMC LPC 2015-02-26 15:54:41 -07:00
Florent Kermarrec
8da1faf310 mibuild: move identifier to platforms 2015-02-26 19:00:43 +01:00
Florent Kermarrec
e6a21b2305 mibuild: fix missing xilinx_common -->xilinx.common change 2015-02-26 14:04:36 +01:00
Florent Kermarrec
bd5ed0977b platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms) 2015-02-26 12:51:57 +01:00
Florent Kermarrec
e27a94e7fc mibuild: add VivadoProgrammer (only load_bitstream) 2015-02-26 12:31:19 +01:00
Florent Kermarrec
b3faf5f0da mibuild: better file organization (create directory for each vendor and move programmers in it) 2015-02-26 12:25:59 +01:00
Yann Sionneau
5bb1c789aa mibuild/kc705: add FMC connectors 2015-02-18 08:32:45 -07:00
Yann Sionneau
cea1551ae0 mibuild: support pin names in IO extensions 2015-02-18 08:32:31 -07:00
Sebastien Bourdeauducq
d51d33af73 mibuild: make resolve_signals public 2015-02-14 03:05:07 -08:00
Florent Kermarrec
beef7425ce mibuild: return verilog namespace with build 2015-02-14 03:02:47 -08:00
Sebastien Bourdeauducq
6fca1dd4dc mibuild/xilinx_vivado: fix list aliasing problem 2014-12-21 17:37:11 +08:00
Florent Kermarrec
8576b91290 xilinx_vivado: add parameters to pass specific commands (to be declared in platforms) 2014-12-21 17:35:42 +08:00
Florent Kermarrec
b87ad1af63 xilinx_vivado: use REM for comment on Windows 2014-11-20 15:27:14 -08:00
Sebastien Bourdeauducq
dff3a17711 mibuild/programmer: add migen folders to flash proxy search dirs 2014-11-05 23:23:22 +08:00
Florent Kermarrec
648ab8fa7a kc705: add Ethernet pins 2014-11-01 21:11:47 +08:00
Florent Kermarrec
c0c04a1878 xilinx_vivado: use .bat on Windows platforms (otherwise Vivado uses Unix scripts...) 2014-11-01 20:59:19 +08:00
Florent Kermarrec
51f699758c xilinx_vivado: add hierarchical utilization report 2014-11-01 20:57:54 +08:00
Florent Kermarrec
dbaeaf7833 remove trailing whitespaces 2014-10-17 17:08:46 +08:00
Robert Jordens
4328122a9c vivado: add more reporting 2014-09-04 15:25:34 +08:00
Robert Jordens
7c19e43444 vivado: mode batch to prevent vivado from opening tcl shell on error 2014-09-04 15:25:34 +08:00
Sebastien Bourdeauducq
f21e05025d platforms/kc705: use jtaghs1_fast cable 2014-09-03 17:29:26 +08:00