080afdc3f9
fhdl/verilog: fix signedness rules for comparison
2013-06-26 22:45:47 +02:00
0224ea01cb
migen/genlib/cordic.py: generic cordic
...
* rotating or vectoring cordic modes
* circular, linear, or hyperbolic functions
* combinatorial, pipelined or iterative evaluation
* arbitrary width, stages and guard bits
* two or four quadrant mode for circular/rotate
2013-06-26 22:31:36 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
b56cb3cefc
fhdl/verilog: improve error reporting
2013-06-24 19:44:25 +02:00
d6f7b4cee6
lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)
2013-06-17 23:36:03 +02:00
5cd0019231
genlib/fifo: support records
2013-06-17 23:35:10 +02:00
6d6d232cad
lasmibus/crossbar: better switching policy
2013-06-15 16:51:09 +02:00
ac2cde0e87
asmibus: remove port sharing
2013-06-14 18:34:36 +02:00
0c52c08989
bus/asmibus: fix slot aging timer
2013-06-14 17:57:43 +02:00
1ec1fb9ebe
bus/lasmibus/Crossbar: support cba_shift=0
2013-06-11 18:15:49 +02:00
fe54c68762
lasmi: fix minor problems
2013-06-10 22:49:33 +02:00
aea3b59432
genlib/fsm: fix handling of zero delayed_enter
2013-06-10 22:49:05 +02:00
3a284b9c1e
actorlib: LASMI DMA (untested)
2013-06-10 22:29:39 +02:00
932bfa7e75
bus: Wishbone -> LASMI bridge (untested)
2013-06-10 18:52:07 +02:00
f2e2397c9d
bus/lasmibus: bugfixes
2013-06-09 23:36:32 +02:00
a836cba790
bus/lasmibus: add target and initiator
2013-06-09 16:03:22 +02:00
35f9f2e9d7
bus/lasmi: interface definition and crossbar (untested)
2013-06-08 15:49:50 +02:00
85813b3b58
csr/sram: fix reads on high addresses when word_bits != 0
2013-06-03 21:52:23 +02:00
e5e3492afe
csr/sram: fix page_bits computation
2013-06-03 21:51:44 +02:00
cebfe787db
genlib/misc: fix import
2013-05-30 18:46:52 +02:00
ebbd5ebcd2
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
2013-05-30 18:45:04 +02:00
f0b0942055
bitreverse: fhdl/tools -> genlib/misc
2013-05-30 18:44:37 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
7ada0159fd
bus/csr/SRAM: support init
2013-05-19 20:53:37 +02:00
792b8fed1b
bus/asmi: port sharing support
2013-05-12 15:58:39 +02:00
f202946717
fhdl/tools/_TargetLister: do not include array keys in targets
2013-05-11 17:28:41 +02:00
0ec6a7eb4e
genlib/record: match_by_position -> connect_flat
2013-05-11 11:48:21 +02:00
955a9733c8
Revert "genlib/record/connect: add match_by_position"
...
This reverts commit df1ed32765
2013-05-10 17:41:51 +02:00
c82b53f1cd
bank/description/AutoCSR: add autocsr_exclude
2013-05-08 20:58:57 +02:00
10212e85e7
dma_asmi: cleanup
2013-05-08 18:58:50 +02:00
b9b6df6f29
bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source
2013-05-08 18:12:26 +02:00
7a74dae461
actorlib/spi: add DMAWriteController
2013-05-04 17:38:54 +02:00
fd089b146f
actorlib/dma_asmi/OOOWriter: fix tag offset
2013-05-04 17:38:17 +02:00
12deaa91d8
flow/network/DataFlowGraph: add_buffered_connection
2013-05-02 13:25:30 +02:00
b5b29f6d5d
bank/description/CSRStorage: set reset property of storage for use in test benches
2013-05-02 11:49:23 +02:00
8ffa273719
flow/network: better determination of plumbing layout
2013-05-01 22:13:26 +02:00
471393d0f9
actorlib/dma_asmi: drive dat_wm
2013-05-01 21:52:26 +02:00
c8810a016f
actorlib/spi: add DMA read controller
2013-04-30 18:55:01 +02:00
c70c71502e
actorlib/spi/SingleGenerator: use CSR alignment bits
2013-04-30 18:54:47 +02:00
dc0304a87b
bank/description/CSRStorage: support alignment bits
2013-04-30 18:53:40 +02:00
51f1ace061
flow/network/CompositeActor: expose unconnected endpoints
2013-04-30 18:53:02 +02:00
4f13c5b74d
flow/network/DataFlowGraph: add add_pipeline
2013-04-30 15:49:51 +02:00
fb83794ef4
actorlib/spi/Collector: cleanup, new APIs
2013-04-28 18:32:46 +02:00
746e452838
actorlib/dma_asmi: support for writes
2013-04-28 18:06:36 +02:00
e97edd7253
genlib/fifo: disable retiming on Gray counter outputs
2013-04-25 14:57:07 +02:00
156ef43ace
genlib/cdc: add NoRetiming
2013-04-25 14:56:45 +02:00
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
67c3119249
genlib/fifo: add asynchronous FIFO
2013-04-25 13:30:37 +02:00
fee228a09f
fhdl/specials/memory: do not write address register for async reads
2013-04-25 13:30:05 +02:00
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
8e11fcf1d0
bus/csr/SRAM: fix Module conversion errors
2013-04-14 13:55:04 +02:00
ea63389823
fhdl: support len() on all values
2013-04-14 13:50:26 +02:00
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
4c9018ea17
fhdl/visit: add TransformModule
2013-04-10 23:42:14 +02:00
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
1cc4c8ee9f
uio: remove Trampoline (Python 3.3 provides generator delegation instead)
2013-04-10 22:15:28 +02:00
6ce856290a
flow: match record fields by position
2013-04-10 21:33:56 +02:00
df1ed32765
genlib/record/connect: add match_by_position
2013-04-10 21:33:45 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
20bdd424c8
flow: adapt to new Record API
2013-04-01 22:15:23 +02:00
29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
633e5e6747
fhdl/module/finalize: pass additional args to do_finalize
2013-03-30 11:29:46 +01:00
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
77a0f0a3bb
actorlib/structuring/Cast: support inversion
2013-03-25 15:54:09 +01:00
c4c4765a4e
bank/csrgen/BankArray: retain name information
2013-03-25 14:44:15 +01:00
53edc3557e
bank/description/Register: add get_size
2013-03-25 14:43:44 +01:00
3da98ea04d
genlib/record: use getattr instead of __dict__
2013-03-24 00:51:01 +01:00
1897b74f97
genlib/record: add eq
2013-03-24 00:50:33 +01:00
9d7c679b8c
genlib/fifo: simple synchronous FIFO
2013-03-22 18:18:38 +01:00
ca431fc7c2
fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
a94bf3b2c5
genlib/cdc/MultiReg: output clock domain defaults to sys
2013-03-21 10:40:02 +01:00
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
e95d2f4779
fhdl/tools/value_bits_sign: support not
2013-03-18 09:52:43 +01:00
b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
2a4cc3875c
Merge pull request #6 from larsclausen/master
...
Minor improvements
2013-03-17 07:33:14 -07:00
2f522bdd9f
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
2013-03-15 19:50:24 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
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Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
72579a6129
Add support for negative slice indices
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In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
Robert Jordens
Kenneth Ryerson
Florent Kermarrec
Lars-Peter Clausen