Commit Graph

4820 Commits

Author SHA1 Message Date
Florent Kermarrec 10146abf0a cpu/rocket: move csr to IO region 2019-10-09 10:24:01 +02:00
Florent Kermarrec 7f1d4623ff build/xilinx/vivado: fix default synth-mode 2019-10-09 10:19:18 +02:00
Florent Kermarrec a4ef9b29b9 soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)
The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.

The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length

It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.
2019-10-09 10:15:42 +02:00
Pascal Cotret e923a88dcc
Update README (related to issue #273)
Following my problems with the quick start guide (issue #273), I suggest a few modifications to have a "real" quick start guide.
2019-10-09 09:48:32 +02:00
enjoy-digital e8b90e8009
Merge pull request #274 from gsomlo/gls-shadow-base
builder: use the SoC's existing shadow base with get_csr_header()
2019-10-08 21:15:54 +02:00
Gabriel Somlo 53777391e8 builder: use the SoC's existing shadow base with get_csr_header()
Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.

Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
2019-10-08 14:28:50 -04:00
Florent Kermarrec 92975b139e targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys 2019-10-07 10:38:26 +02:00
Florent Kermarrec 4a1cefe946 build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode 2019-10-07 10:37:16 +02:00
Florent Kermarrec 3e22d4b9e6 xilinx/common: be sure language is not vhdl when yosys synthesis is used 2019-10-07 10:36:32 +02:00
Florent Kermarrec 975bd9be8b cpu/vexriscv: use specific mem_map for linux variant 2019-10-07 08:50:03 +02:00
enjoy-digital 2dfe7441d6
Merge pull request #271 from gsomlo/gls-yosys-nowidelut
RFC: optional '-nowidelut' flag for yosys synth_ecp5
2019-10-06 14:55:44 +02:00
Gabriel L. Somlo 6aa76b1df8 trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).

Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-06 08:37:43 -04:00
enjoy-digital c954ff0cfa
Merge pull request #272 from sergachev/fix-comments
fix comments in icap.py
2019-10-06 12:10:19 +02:00
Ilia Sergachev 2f7bd97129 fix comments 2019-10-06 10:47:28 +02:00
Florent Kermarrec ab4a5d1dc1 litex_setup: add litejesd204b 2019-10-04 10:00:45 +02:00
enjoy-digital 960b25a541
Merge pull request #270 from gsomlo/gls-csr-upper
soc/integration: ensure CSR constants are in uppercase
2019-10-01 21:40:56 +02:00
Florent Kermarrec 41ad08e8ef soc/cores/icap: simplify ICAPBitstream (untested) 2019-10-01 21:30:14 +02:00
Florent Kermarrec 0c2993866c soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP 2019-10-01 21:04:49 +02:00
enjoy-digital 4bb2827e05
Merge pull request #269 from antmicro/rework_icap
soc: cores: support sending custom bitstream to ICAP
2019-10-01 20:55:28 +02:00
Gabriel Somlo c8790d342a soc/integration: ensure CSR constants are in uppercase
Fixup over commit 8be5824e.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-01 12:15:25 -04:00
Jan Kowalewski 4423a46ba2 soc: cores: support sending custom bitstream to ICAP
This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
2019-10-01 13:44:45 +02:00
Florent Kermarrec 427d7af767 soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00
Florent Kermarrec 59bf04d965 soc/interconnect/stream: add separators, mode Actor modules just after Endpoint 2019-09-30 23:33:25 +02:00
Florent Kermarrec 59995c5359 soc_zynq: update get_csr_header 2019-09-30 16:00:11 +02:00
Florent Kermarrec 4d90058b18 soc/integration: move cpu_interface retro-compatibility to litex/__init__ 2019-09-30 11:32:07 +02:00
Florent Kermarrec 8be5824e25 soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses 2019-09-30 10:59:36 +02:00
Florent Kermarrec 7b72148c4e cpu: remove initial SERV support (we'll work in a branch to experiment with it) 2019-09-30 08:35:18 +02:00
Florent Kermarrec 63a813af9c soc_core: fix cpu_type=None case and add test for it 2019-09-30 08:26:38 +02:00
Florent Kermarrec 3d257d7266 soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.
Proper AXI support will be added in the future for SoCs.
2019-09-29 17:33:16 +02:00
Florent Kermarrec e8e57b4f87 soc_core: cleanup/re-align 2019-09-29 17:31:37 +02:00
Florent Kermarrec 334ae336bf soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators 2019-09-29 17:23:26 +02:00
Florent Kermarrec 241c3c642b test/test_targets: update cpu-type to mor1kx 2019-09-29 17:12:15 +02:00
Florent Kermarrec 48e5a1d140 soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
Florent Kermarrec e9ed4761b5 soc/cores/gpio: uniformize with others cores 2019-09-29 16:10:44 +02:00
Florent Kermarrec 78cecbe36b soc/cores: rename frequency_meter to freqmeter and uniformize with others cores 2019-09-29 16:08:39 +02:00
Florent Kermarrec 7575ecc6ad soc/cores/ecc: improve readibility, uniformize with others cores 2019-09-29 16:02:04 +02:00
Florent Kermarrec c6fe3f3145 soc/cores/clocks: improve readibility 2019-09-29 15:58:22 +02:00
Florent Kermarrec 6fcb12a98f soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) 2019-09-29 15:47:10 +02:00
Florent Kermarrec b826c1705f soc/cores/cpus: improve ident/align, uniformize between cpus 2019-09-29 15:41:36 +02:00
Florent Kermarrec 355072c285 soc/cores/cpu: add CPU class and make all CPU inheritate from it
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
2019-09-29 15:27:41 +02:00
Florent Kermarrec 2c3ad3f96d soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) 2019-09-29 14:44:44 +02:00
Florent Kermarrec 101f1b1cef soc/integration: add common.py and move helpers from soc_core to it 2019-09-29 14:22:26 +02:00
Florent Kermarrec 68ba1c60be soc_core: avoid manual listing of support CPUs, just use CPU.keys() 2019-09-28 22:19:23 +02:00
Florent Kermarrec 9095b80e89 soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) 2019-09-28 19:01:41 +02:00
Florent Kermarrec 8dd2dc1ce8 integration/soc_core: remove csr_map_update (no longer used) 2019-09-28 18:59:30 +02:00
Florent Kermarrec da91aa43f7 soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done 2019-09-28 14:15:48 +02:00
Florent Kermarrec 8099b0beb6 soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter 2019-09-28 12:35:41 +02:00
Florent Kermarrec 7660dc22e1 soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) 2019-09-28 12:09:55 +02:00
Florent Kermarrec a3816096a7 cores/cpu: define CPUS and simplify instance 2019-09-28 00:55:08 +02:00
Florent Kermarrec 9f6a2ae73e soc_core/serv: use UART_POLLING (no interrupt support) 2019-09-28 00:42:00 +02:00