320dffb4ac
sim: memory access from generators
2015-09-20 14:52:26 +08:00
59802bec76
fhdl/structure: add missing init
2015-09-20 14:46:30 +08:00
1861ae9d01
fhdl/specials: MemoryPort.clock should always be a ClockSignal
2015-09-19 23:21:24 +08:00
262fd50677
fhdl/simplify: add MemoryToArray
2015-09-19 23:20:57 +08:00
776579f0d7
fhdl/structure: all case statements should be lists
2015-09-17 17:22:24 +08:00
bcf62997f6
fhdl/bitcontainer: remove fiter
2015-09-17 17:22:03 +08:00
c2109f8f81
minor bugfixes
2015-09-17 15:20:27 +08:00
9dd3200ba2
fhdl/structure: fix namespace pollution
2015-09-17 14:39:17 +08:00
0a92e346d3
fhdl/bitcontainer: remove fslice and freversed
2015-09-17 14:38:33 +08:00
f5ab734bdf
fhdl/verilog: fix case value sort
2015-09-17 08:03:48 +08:00
e940c6d9b9
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
2015-09-15 12:38:02 +08:00
42afba2bbc
fhdl/decorators: remove traces of deprecated API
2015-09-12 19:44:35 +08:00
1bdb9bee22
fhdl/decorators: remove deprecated API
2015-09-12 19:34:44 +08:00
336728413a
simplify imports, migen.fhdl.std -> migen
2015-09-12 19:34:07 +08:00
49ef182305
fhdl/tools: add input lister
2015-09-10 20:33:10 -07:00
f9849fb8be
style
2015-09-10 20:32:47 -07:00
714ae43ab8
fhdl: remove features new simulator won't use
2015-09-10 18:29:57 -07:00
1dcd2ac1c0
fixed bug in value_bits_sign of mul operatiors
2015-09-10 10:53:26 -07:00
f32f9be17a
resetless -> reset_less
2015-07-27 11:46:11 +08:00
cc6877df9e
fhdl: allow use of ResetSignal() on resetless clock domains
2015-07-27 01:51:52 +08:00
1f1ff5a5e9
migen/fhdl/tools: fix rename_clock_domain when new == old
...
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
a5f495aeac
fhdl/verilog: add reserved keywords
2015-05-23 14:01:08 +02:00
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
...
This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
...
This reverts commit ea04947519
2015-03-30 19:41:13 +08:00
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
...
This reverts commit 95cfc444e6
2015-03-30 19:41:04 +08:00
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
7fa1cd72a8
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
5a9afee234
fhdl/specials/memory: use $readmemh to initialize memories
2015-03-18 15:27:01 +01:00
c0fb0ef600
fhdl/verilog: change the way we initialize reg: reg name = init_value;
...
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
...
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
...
This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
2015-03-18 12:08:25 +01:00
b7d7fe1a4c
fhdl/special: add optional synthesis directive (needed by Synplify Pro)
2015-03-17 14:59:05 +01:00
Sebastien Bourdeauducq
Yves Delley
Florent Kermarrec
Guy Hutchison
Robert Jordens