367b510590
Merge pull request #838 from jersey99/ussysmon
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Ussysmon: SYSMONE1 for US devices
2021-03-15 10:19:54 +01:00
13e13a094c
soc/interconnect/axi: Add AXILite Clock Domain Crossing module.
2021-03-15 10:18:12 +01:00
11f7416e36
Merge pull request #847 from zoobab/master
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Add support for xcompiler on Alpine 3.13
2021-03-12 21:49:44 +01:00
0456de50aa
Add support for xcompiler on Alpine 3.13
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Problem: xcompiler on Alpine 3.13 was not found
Solution is to add "riscv-none-elf-gcc":
1. Add Edge to your repositories:
$ echo -e "http://dl-cdn.alpinelinux.org/alpine/edge/main\nhttp://dl-cdn.alpinelinux.org/alpine/edge/testing\nhttp://dl-cdn.alpine
linux.org/alpine/edge/community" >> /etc/apk/repositories
$ apk update
$ apk add gcc-riscv-none-elf
2. The xcompiler should be found at:
$ which riscv-none-elf-gcc
/usr/bin/riscv-none-elf-gcc
2021-03-12 20:13:23 +01:00
1e9606f3fb
software/liblitedram: Improve find_cmd_delay to favor higher number of valid modules and centered scan.
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Also add an optional debug #define to look at cmd/clk centering scans:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 12 2021 14:06:20
BIOS CRC passed (116682af)
Migen git sha1: 7014bdc
LiteX git sha1: edcc0f88
--=============== SoC ==================--
CPU: VexRiscv @ 125MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
tCK/4 taps: 6
Cmd/Clk scan (0-12)
|Cmd/Clk delay: 0
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: -
m5: |11111111110000000000000111| delay: -
m6: |11111111111000000000000001| delay: -
m7: |11111111111000000000000011| delay: -
Delay mean: 22, ideal: 13
Cmd/Clk delay: 1
m0: |11100000000000001111111111| delay: 16
m1: |10000000000000011111111111| delay: 15
m2: |11111000000000000011111111| delay: 18
m3: |11111000000000000001111111| delay: 19
m4: |11111111111000000000000011| delay: -
m5: |11111111111000000000000011| delay: -
m6: |11111111111100000000000000| delay: -
m7: |11111111111100000000000001| delay: -
Delay mean: 23, ideal: 13
Cmd/Clk delay: 2
m0: |11110000000000000111111111| delay: 17
m1: |11000000000000001111111111| delay: 16
m2: |11111100000000000001111111| delay: -
m3: |11111100000000000000111111| delay: -
m4: |11111111111100000000000001| delay: -
m5: |11111111111100000000000001| delay: -
m6: |11111111111110000000000000| delay: -
m7: |11111111111110000000000000| delay: -
Delay mean: 22, ideal: 13
Cmd/Clk delay: 3
m0: |11111000000000000011111111| delay: 18
m1: |11100000000000000111111111| delay: 17
m2: |11111110000000000000111111| delay: -
m3: |11111110000000000000011111| delay: -
m4: |11111111111110000000000000| delay: -
m5: |11111111111110000000000000| delay: -
m6: |01111111111111000000000000| delay: 01
m7: |01111111111111000000000000| delay: 01
Delay mean: 15, ideal: 13
Cmd/Clk delay: 4
m0: |11111100000000000001111111| delay: -
m1: |11110000000000000011111111| delay: 18
m2: |11111111000000000000011111| delay: -
m3: |11111111000000000000001111| delay: -
m4: |11111111111111000000000000| delay: -
m5: |11111111111111000000000000| delay: -
m6: |00111111111111100000000000| delay: 02
m7: |00111111111111100000000000| delay: 02
Delay mean: 13, ideal: 13
Cmd/Clk delay: 5
m0: |11111110000000000000111111| delay: -
m1: |11111000000000000001111111| delay: 19
m2: |11111111100000000000001111| delay: -
m3: |11111111100000000000000111| delay: -
m4: |01111111111111100000000000| delay: 01
m5: |01111111111111100000000000| delay: 01
m6: |00011111111111110000000000| delay: 03
m7: |00011111111111110000000000| delay: 03
Delay mean: 11, ideal: 13
Cmd/Clk delay: 6
m0: |11111111000000000000011111| delay: -
m1: |11111100000000000000111111| delay: -
m2: |11111111110000000000000111| delay: -
m3: |11111111110000000000000011| delay: -
m4: |00111111111111110000000000| delay: 02
m5: |00011111111111110000000000| delay: 03
m6: |00001111111111111000000000| delay: 04
m7: |00001111111111111000000000| delay: 04
Delay mean: 9, ideal: 13
Cmd/Clk delay: 7
m0: |11111111100000000000001111| delay: -
m1: |11111110000000000000011111| delay: -
m2: |11111111111000000000000011| delay: -
m3: |11111111111000000000000001| delay: -
m4: |00011111111111111000000000| delay: 03
m5: |00001111111111111000000000| delay: 04
m6: |00000111111111111100000000| delay: 05
m7: |00000111111111111100000000| delay: 05
Delay mean: 10, ideal: 13
Cmd/Clk delay: 8
m0: |11111111110000000000000111| delay: -
m1: |11111111000000000000001111| delay: -
m2: |11111111111100000000000001| delay: -
m3: |11111111111100000000000000| delay: -
m4: |00001111111111111100000000| delay: 04
m5: |00000111111111111100000000| delay: 05
m6: |00000011111111111110000000| delay: 06
m7: |00000011111111111110000000| delay: 06
Delay mean: 11, ideal: 13
Cmd/Clk delay: 9
m0: |11111111111000000000000011| delay: -
m1: |11111111100000000000000111| delay: -
m2: |11111111111110000000000000| delay: -
m3: |11111111111110000000000000| delay: -
m4: |00000111111111111110000000| delay: 05
m5: |00000011111111111110000000| delay: 06
m6: |00000001111111111111000000| delay: 07
m7: |00000001111111111111000000| delay: 07
Delay mean: 12, ideal: 13
Cmd/Clk delay: 10
m0: |11111111111100000000000011| delay: -
m1: |11111111110000000000000011| delay: -
m2: |01111111111111000000000000| delay: 01
m3: |01111111111111000000000000| delay: 01
m4: |00000011111111111111000000| delay: 06
m5: |00000001111111111111000000| delay: 07
m6: |00000000111111111111100000| delay: 08
m7: |00000000111111111111100000| delay: 08
Delay mean: 11, ideal: 13
Cmd/Clk delay: 11
m0: |11111111111110000000000001| delay: -
m1: |11111111111000000000000001| delay: -
m2: |00111111111111100000000000| delay: 02
m3: |00111111111111100000000000| delay: 02
m4: |00000001111111111111100000| delay: 07
m5: |00000000111111111111100000| delay: 08
m6: |00000000011111111111110000| delay: 09
m7: |00000000011111111111110000| delay: 09
Delay mean: 12, ideal: 13
| best: 11
Setting Cmd/Clk delay to 11 taps.
Data scan:
m0: |11111111111110000000000001| delay: -
m1: |11111111111000000000000001| delay: -
m2: |00111111111111100000000000| delay: 02
m3: |00111111111111100000000000| delay: 02
m4: |00000001111111111111100000| delay: 07
m5: |00000000111111111111100000| delay: 08
m6: |00000000011111111111110000| delay: 09
m7: |00000000011111111111110000| delay: 09
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |11111111100000000000000000000000| delays: 04+-04
m0, b4: |00000000000001111111110000000000| delays: 17+-04
m0, b5: |00000000000000000000000000111111| delays: 29+-03
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b03 delays: 04+-04
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111111000000000000000000000000| delays: 04+-04
m1, b4: |00000000000011111111100000000000| delays: 16+-04
m1, b5: |00000000000000000000000000111111| delays: 29+-03
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 16+-04
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11111110000000000000000000000000| delays: 03+-03
m2, b4: |00000000000111111111000000000000| delays: 15+-04
m2, b5: |00000000000000000000000011111111| delays: 28+-04
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 15+-04
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11111110000000000000000000000000| delays: 03+-03
m3, b4: |00000000001111111110000000000000| delays: 14+-04
m3, b5: |00000000000000000000000011111111| delays: 28+-04
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 14+-04
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |10000000000000000000000000000000| delays: -
m4, b4: |00001111111110000000000000000000| delays: 08+-04
m4, b5: |00000000000000000111111111000000| delays: 22+-05
m4, b6: |00000000000000000000000000000001| delays: 31+-00
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 08+-04
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00001111111110000000000000000000| delays: 08+-04
m5, b5: |00000000000000000011111111000000| delays: 22+-04
m5, b6: |00000000000000000000000000000001| delays: 31+-00
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 08+-04
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00111111110000000000000000000000| delays: 06+-04
m6, b5: |00000000000000111111111000000000| delays: 18+-04
m6, b6: |00000000000000000000000000001111| delays: 30+-02
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 19+-04
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |01111111111100000000000000000000| delays: 06+-05
m7, b5: |00000000000000011111111110000000| delays: 20+-05
m7, b6: |00000000000000000000000000001111| delays: 30+-02
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 06+-05
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 40MiB/s
Read speed: 33MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
2021-03-12 14:34:49 +01:00
3cbdc567ff
soc: Add init_rom to initialize ROM and contents and with auto_size option (enable by default) to reduce ROM size to length of contents when in Read Only mode.
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This ensures the integrated ROM is reduced to minimal size before build and avoid having to adjust it manually with --integrated-rom-size on targets.
2021-03-12 09:42:59 +01:00
d9b6d7608c
soc/integration/soc_core: Cleanup SoCCore arguments.
2021-03-12 09:03:17 +01:00
21273ffe87
soc/integration/builder: Cleanup and add comments.
2021-03-11 16:21:45 +01:00
cba4642444
Merge pull request #845 from meklort/meklort/xics-fix
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xics: Disable endianness swapping
2021-03-11 13:33:15 +01:00
a81d1da980
soc/integration/common: Improve get_mem_data error reporting.
2021-03-11 10:19:36 +01:00
26f55797cc
software/liblitedram: Make sure init_error is set before init_done.
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Useful for standalone core where the user logic can be looking at init_done/init_error to
condition user accesses.
2021-03-10 19:41:02 +01:00
da1277021a
build/generic_platform: Minor cosmetic cleanups.
2021-03-10 19:21:02 +01:00
10eff37b84
interconnect/axi: Fix AXILiteDownverterWrite/Read base address.
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Downconverter should start on master's addr, not on aligned master's addr.
2021-03-10 18:54:02 +01:00
08072eb872
xics: Disable endianness swapping
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The endianess swapping code caused the core to diverge from microwatt resulting in:
- The xics tests not working as-is: https://github.com/antonblanchard/microwatt/blob/master/tests/xics/xics.h
- byte writes writing to the incorrect byte
This removes endianswapping and minimizes the delta from upstream for the xics irq.h header.
2021-03-10 07:39:19 -07:00
c92e4cb3ca
xics: Ass missing static keywords to irq header.
2021-03-10 07:32:24 -07:00
9d08c65e8a
build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists.
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In simulation, default_clk_period is not necessarily required.
2021-03-10 12:25:35 +01:00
ee2d373477
Merge pull request #843 from gregdavill/monitor_token_fix
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cores/stream/monitor: Fix typo
2021-03-10 11:00:55 +01:00
e48b269d77
build/generic_platform: Fix use_default_clk set when not user provided sys_clk.
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Prevented the default timing constraint to be generated in the timing constraint file.
2021-03-10 10:47:22 +01:00
31cc7f1e42
cores/stream/monitor: Fix typo
2021-03-10 09:11:07 +10:30
0e7d8219ea
soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate.
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Ex of instance:
from litex.soc.cores import gpio
gpio_in_pads = Signal(16)
self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True)
self.add_csr("gpio_in")
2021-03-09 13:57:48 +01:00
0d8b6f8fbb
csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection.
2021-03-09 13:55:43 +01:00
ece9005949
cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).
2021-03-09 09:07:52 +01:00
834c90b71f
Merge pull request #841 from gatecat/radiant_pins_x
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build/radiant: Skip location constraint for X pins
2021-03-08 16:30:22 +01:00
c64e2d3a85
build/radiant: Skip location constraint for X pins
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:27:32 +00:00
5af8e5c934
soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.
2021-03-08 13:50:22 +01:00
6bb0541f9a
Remove ussysmon.py as it is consolidated inside xadc.py
2021-03-06 14:31:24 -08:00
a1e54671be
sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation.
2021-03-06 17:36:21 +01:00
7e3912aaef
software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature.
2021-03-06 17:31:07 +01:00
647d3eb51a
soc/cores/xadc.py: Move ussysmon here
2021-03-06 08:14:13 -08:00
31ac6659c9
cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series.
2021-03-05 14:30:28 +01:00
9624cce188
cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.
2021-03-05 14:27:08 +01:00
0280a9dd57
soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer.
2021-03-05 14:23:39 +01:00
8b531b4215
cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.
2021-03-04 19:32:41 +01:00
10d87e4138
cores/video/VideoPHYs: Use IO primitives.
2021-03-04 18:22:34 +01:00
82d0ecd7bd
cores/video/VideoTerminal: Add CLEAR-XY after reset.
2021-03-04 17:55:37 +01:00
a1e7aab35c
cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes.
2021-03-04 14:42:50 +01:00
60e2d3335f
cores/clock/xilinx_us: Remove USP modules (refactoring issue).
2021-03-04 14:42:03 +01:00
2d5b4b206b
bios: Add VideoFrameBuffer VTG/DMA initialisation.
...
This just configures the enables for now since other parameters are pre-configured
during the build.
2021-03-04 12:01:32 +01:00
f553b5fc83
soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600.
2021-03-04 11:59:44 +01:00
0ee92448b9
soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader).
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Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.
2021-03-04 11:53:43 +01:00
225a518f7e
soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.
2021-03-04 08:40:47 +01:00
ae5f67f6f0
litex/soc/cores/ussysmon.py: minor bug
2021-03-03 14:47:52 -08:00
1793efb50b
litex/soc/cores/ussysmon.py: dadr address space bump
2021-03-03 14:38:27 -08:00
ccc8916995
soc/cores/video: Add initial (and simple) VideoFrameBuffer core.
2021-03-03 19:58:11 +01:00
922f85e64b
litex/soc/cores/ussysmon.py: ADC transfer function
2021-03-03 10:50:58 -08:00
24fb153fa1
soc/integration: Add add_video_terminal method to LiteXSoC.
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Adds the new LiteX's VideoTerminal core to the SoC:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
2021-03-03 17:45:02 +01:00
35ffba8801
soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.
2021-03-03 16:17:12 +01:00
c5ee6741a0
software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).
2021-03-03 11:32:43 +01:00
d3407c67b1
build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.
2021-03-03 09:25:54 +01:00
134c628357
cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.
2021-03-03 09:15:51 +01:00
enjoy-digital
Benjamin Henrion
Evan Lojewski
Greg Davill
gatecat
Vamsi Vytla