416afd3109
add doc comment for event
2020-02-06 17:56:21 +08:00
33d9e45a8b
fix formatting on spiopi
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Pycharm really butchered the code when I did a copy-and-paste...
it has questionable default formatting preferences.
2020-02-06 17:54:26 +08:00
cc6ed667df
Request to merge I2S and SPIOPI cores
2020-02-06 17:25:00 +08:00
ae085782ae
doc: add lxsocdoc.md (README from lxsocdoc repository)
2020-02-05 11:06:57 +01:00
5ff02e23a0
Merge pull request #375 from xobs/add-lxsocdoc
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Add lxsocdoc
2020-02-05 10:15:21 +01:00
1944d8d9d0
bios/main: add LiteX tagline
2020-02-04 19:14:23 +01:00
40cddca933
Merge pull request #376 from antmicro/build-sim-do-not-override-C-LD-FLAGS
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build/sim: allow to use environment's {C,LD}FLAGS
2020-02-04 18:19:33 +01:00
90fe585003
build/sim: allow to use environment's {C,LD}FLAGS
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There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
2020-02-04 17:31:31 +01:00
58598d4fda
integration: svd: move svd generation to `export`
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It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h. This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 23:49:08 +08:00
73ed7e564c
soc: doc: use sphinx toctree as it was intended
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The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely. This patch causes it to be used correctly,
which removes the need for double-including various sections.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:34:10 +08:00
7c3bc0b09f
litex-doc: initial merge of lxsocdoc
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lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.
This merges the existing lxsocdoc distribution into the `soc/doc` directory.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:14:41 +08:00
bd6fd3da55
Merge pull request #373 from antmicro/l2-reverse
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tools/litex_sim: use l2_reverse flag
2020-02-03 12:55:48 +01:00
f3b068e2ee
tools/litex_sim: use l2_reverse flag
2020-02-03 12:03:57 +01:00
3350d33f9c
wishbone/Cache: add reverse parameter
2020-01-31 19:31:33 +01:00
eff9caee6a
soc_sdram: add l2_reverse parameter
2020-01-31 19:18:07 +01:00
6e5b47f4c6
Merge pull request #370 from Disasm/fixes
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Small fixes
2020-01-31 18:27:26 +01:00
de88ed282a
Fix argument descriptions
2020-01-31 18:54:25 +03:00
eb49ec217e
Pass --csr-json to the Builder
2020-01-31 18:53:50 +03:00
b69f2993e4
soc_core: add UART bridge support (simplify having to do it externally)
2020-01-31 15:12:18 +01:00
7a6c04db9e
build/altera/quartus: fix fmt_r typo
2020-01-30 13:55:13 +01:00
c6b9676db8
cpu/minerva: update (use new nMigen API)
2020-01-30 13:42:02 +01:00
9d2894727e
inteconnect/stream: use PipeValid implementation for Buffer
2020-01-30 09:36:04 +01:00
1c88c0f896
inteconnect/stream: cleanup
2020-01-30 09:32:04 +01:00
cafd9c358a
Merge pull request #366 from gsomlo/gls-csr-followup
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software, integration/export: (re-)expose CSR subregister accessors
2020-01-30 08:18:12 +01:00
ff2775c264
software, integration/export: (re-)expose CSR subregister accessors
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Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.
This restores downstream ability to override CSR handling at the
subregister accessor level.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-29 14:29:24 -05:00
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
b22ad1acfb
build/xilinx/vivado: improve readability of generated tcl/xdc files
2020-01-29 16:27:18 +01:00
7bc34a9bc7
integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).
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When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
2020-01-29 08:31:41 +01:00
b4b56db4e3
Merge pull request #363 from antmicro/litex-sim-ddr4
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tools/litex_sim: add ddr4 PhySettings
2020-01-28 15:36:24 +01:00
c02dd5e8f9
tools/litex_sim: add ddr4 PhySettings
2020-01-28 14:28:24 +01:00
0820adbda1
tools/litex_sim: add --sdram-init parameter
2020-01-27 21:30:13 +01:00
01ae10b803
software/bios: revert M-Labs MiSoC copyright.
2020-01-27 13:12:37 +01:00
ea5ef8c1be
README: update copyright year and make sure LICENSE/README both mention MiSoC
2020-01-27 12:15:11 +01:00
95cfa6a82c
platforms/netv2: add pcie pins
2020-01-27 08:25:57 +01:00
f9bc98ed4c
Merge pull request #359 from gregdavill/bios_ddr3_ecp5
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soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
2020-01-26 11:44:14 +01:00
1f43906236
soc/software/bios/sdram: ECP5 move strobe dly_sel
2020-01-26 09:55:38 +10:30
f84f57d651
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
2020-01-25 13:11:39 +10:30
52765488b5
tools/litex_sim: update copyrights and cosmetic changes
2020-01-24 13:58:49 +01:00
b280bb2ff2
Merge pull request #358 from antmicro/litex_sim_ddr
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tools/litex_sim: add support for other sdram types
2020-01-24 13:33:03 +01:00
9aa97c2e0c
tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3)
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Right now litex_sim supports only SDR memories because it uses hardcoded
PhySettings. With this change PhySettings will be generated based on
selected sdram type which will allow us to use all the different types
of sdram chips in simulation.
2020-01-24 12:30:35 +01:00
19ef19ce0d
cores/clock/create_clkout: rename clk_ce to ce, improve error reporting
2020-01-24 09:10:31 +01:00
7e08836062
Merge pull request #357 from betrusted-io/add_clk_ce
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Add clk ce
2020-01-24 09:01:57 +01:00
1f7549b4c0
add BUFIO to clockgen buffer options
2020-01-24 15:01:13 +08:00
b3f9aa11be
add option for BUFGCE to the clock generator buffer types
2020-01-24 14:58:51 +08:00
cbc081c43d
tools/litex_sim: review/cleanup sdram-module/sdram-data-width features.
2020-01-23 15:42:47 +01:00
b35ea459e7
Merge pull request #354 from antmicro/litex_sim_ddr
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tools/litex_sim: specify dram chip and data width via commandline
2020-01-23 15:34:53 +01:00
674cfcde7d
tools/litex_sim: specify dram chip and data width via commandline
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litex_sim used a single predefined DRAM chip, with this it is now
possible to specify which one to use with --sdram-module and also
its data bus width can be set using --sdram-data-width
2020-01-23 14:41:37 +01:00
b23f13d960
Merge pull request #351 from antmicro/fix_sram_size_argument
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Fix sram size argument
2020-01-23 14:16:02 +01:00
7a05353aa7
soc_core: rename integrated_sram_size argument
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To keep a consistent naming scheme across all arguments.
2020-01-23 13:46:09 +01:00
c4bb4169f1
soc_core: fix integrated_sram_size argument type
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Right now it's kept as a string and crashes
when trying to do math operations on it.
2020-01-23 13:45:16 +01:00
bunnie
Sean Cross
enjoy-digital
Mariusz Glebocki
Piotr Binkowski
Vadim Kaushan
Gabriel Somlo
Greg Davill
Mateusz Holenko