Florent Kermarrec
485934edc9
doc/socdoc: fix example
2020-02-20 19:47:15 +01:00
Florent Kermarrec
53ee9a5e05
cpu/blackparrot: first cleanup pass
2020-02-20 18:50:13 +01:00
Florent Kermarrec
f3829cf081
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
2020-02-20 16:16:36 +01:00
Florent Kermarrec
3a6f97fff3
build/sim: add Verilator FST tracing support.
2020-02-20 13:53:31 +01:00
enjoy-digital
8a715f3b12
Merge pull request #390 from gsomlo/gls-add-sdcard
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Import LiteSDCard support in to LiteX, using nexys4ddr as the initial test target
2020-02-20 08:17:54 +01:00
Gabriel Somlo
516cf40506
targets/nexys4ddr: add optional sdcard support
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Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
d4d2b7f7c6
bios: add litesdcard test routines to boot menu
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This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
7a2e33b817
targets/nexys4ddr: add ethernet via method instead of inheritance
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Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Florent Kermarrec
774a55a2aa
soc_core: fix missing init on main_ram
2020-02-19 14:59:58 +01:00
enjoy-digital
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets
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bios/boot: allow to customize flash offsets of Linux images
2020-02-18 17:54:13 +01:00
Florent Kermarrec
00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
Mateusz Holenko
659c244a0b
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 13:38:09 +01:00
Florent Kermarrec
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
Florent Kermarrec
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00
Florent Kermarrec
854e7cc908
integration/soc: improve Region logger
2020-02-18 08:27:59 +01:00
Florent Kermarrec
9cb8f68e82
bios/boot: update and fix flashboot, improve verbosity
2020-02-17 19:21:54 +01:00
Florent Kermarrec
6ed0f445b6
soc: increase supporteds address_width/paging
2020-02-17 08:36:40 +01:00
Florent Kermarrec
5b3808cb81
soc_core: expose CSR paging
2020-02-17 08:34:10 +01:00
Florent Kermarrec
0497f3ca71
soc/csr_bus: improve CSR paging genericity
2020-02-17 08:28:56 +01:00
Florent Kermarrec
351896bf57
tools/litex_sim: use new sdram verbosity parameter
2020-02-16 16:09:06 +01:00
Florent Kermarrec
67e8a042f8
integration/soc: add configurable CSR Paging
2020-02-16 12:32:05 +01:00
Florent Kermarrec
6576470179
soc_core: add back identifier
2020-02-15 19:04:47 +01:00
enjoy-digital
8f6114d0cd
Merge pull request #387 from BracketMaster/master
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litex_sim now working on MacOS and Linux
2020-02-15 17:05:50 +01:00
Yehowshua Immanuel
3da204edd6
update to work with mac
2020-02-15 10:37:39 -05:00
Florent Kermarrec
3574b90924
tools/litex_sim: specify default local/remote-ip addresses.
2020-02-15 14:04:44 +01:00
Florent Kermarrec
aebaea7764
tools/litex_sim: add ethernet local/remote-ip arguments.
2020-02-15 14:01:56 +01:00
Florent Kermarrec
18a9d4ff2f
interconnect/stream: cleanup imports/idents
2020-02-14 08:08:19 +01:00
enjoy-digital
57fb3720e2
Merge pull request #386 from antmicro/sdram-timing-checker
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tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 16:53:12 +01:00
Piotr Binkowski
eff85a99bb
tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 14:45:15 +01:00
Florent Kermarrec
e4712ff7f3
soc_core: fix cpu_variant renaming regression
2020-02-13 08:34:39 +01:00
Sean Cross
a2f1683b97
doc: rename lxsocdoc -> socdoc and update readme
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With the merge of lxsocdoc into upstream litex, the old name of
"lxsocdoc" doesn't make as much sense. Additionally, the import paths
are now different.
Rename this file to reflect the new home of `soc/doc`, and update the
code examples to work with the new name.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:47:58 +08:00
Sean Cross
baa29f1b03
doc: fix regression with new irq manager
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Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts. This has been subsumed
into a more general `irq` object that manages the interrupts.
Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.
This fixes #385 .
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:32:44 +08:00
Florent Kermarrec
1620f9c5b0
soc/CSR: show alignment in report and add info when updating.
2020-02-12 21:55:30 +01:00
Florent Kermarrec
5b34f4cd34
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
2020-02-12 21:25:52 +01:00
Florent Kermarrec
2f69f607e3
integration/soc: fix refactoring issues
2020-02-12 18:16:38 +01:00
Florent Kermarrec
1d6ce66bf7
soc/integration/builder: update copyright, align arguments
2020-02-12 16:43:11 +01:00
enjoy-digital
98ae91ada5
Merge pull request #383 from Xiretza/builder-directories
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Unify output directory handling in builder
2020-02-12 16:38:04 +01:00
Xiretza
b56545791c
Unify output directory handling in builder
2020-02-12 15:47:16 +01:00
enjoy-digital
4a15c3e219
Merge pull request #382 from enjoy-digital/new_soc
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Add new SoC/LiteXSoC classes and use it for SoCCore/SoCSDRAM
2020-02-11 18:39:33 +01:00
Florent Kermarrec
e9c665a539
soc_core/soc_sdram: add disclaimer
2020-02-11 18:28:05 +01:00
Florent Kermarrec
5558865cbf
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
2020-02-11 18:21:41 +01:00
Florent Kermarrec
1b5caf56fb
soc: fix busword typo
2020-02-11 17:57:05 +01:00
Florent Kermarrec
8b5cc34553
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:44:24 +01:00
enjoy-digital
240a55bace
Merge branch 'master' into new_soc
2020-02-11 17:22:06 +01:00
Florent Kermarrec
d5ad1d56f2
soc/integration: move mem_decoder to soc_core
2020-02-11 17:19:22 +01:00
Florent Kermarrec
0a737cb624
soc/integration/common: simplify get_version
2020-02-11 17:16:24 +01:00
Florent Kermarrec
399b65fa17
soc/add_uart: fix bridge
2020-02-11 16:55:37 +01:00
Florent Kermarrec
160c55d1d4
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
2020-02-11 16:44:25 +01:00
Florent Kermarrec
b2c66b1efd
soc: avoid double definition of main_ram
2020-02-11 16:39:37 +01:00
Florent Kermarrec
5f9946085b
soc: improve log colors on error reporting
2020-02-11 16:24:57 +01:00
