Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,000 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

4000 Commits

Author SHA1 Message Date
Florent Kermarrec c38d8175b7 interconnect/stream: add missing part of Demultiplexer 2015-10-05 00:10:55 +02:00
Sebastien Bourdeauducq af3723db14 setup: add entry points 2015-10-05 00:45:02 +08:00
Sebastien Bourdeauducq 5e8c4cc364 setup: fix readme 2015-10-05 00:44:50 +08:00
Sebastien Bourdeauducq 70e3280579 travis/conda: build for python 3.5 2015-10-05 00:25:25 +08:00
Sebastien Bourdeauducq 09bef1a016 travis/conda: build for python 3.5 2015-10-05 00:10:04 +08:00
Sebastien Bourdeauducq b1f8aa2a67 travis: activate py35 2015-10-04 23:12:07 +08:00
Sebastien Bourdeauducq d983782bed travis: activate py35 2015-10-04 23:11:16 +08:00
Sebastien Bourdeauducq 6258257573 travis: python 3.5 2015-10-04 23:08:29 +08:00
Sebastien Bourdeauducq 4ccb489036 travis: python 3.5 2015-10-04 23:08:14 +08:00
Sebastien Bourdeauducq 9c905830dc sdram: cleanup 2015-10-02 11:37:22 +08:00
Sebastien Bourdeauducq d21358fc26 liteeth_mini: fix imports, replace Counter and FlipFlop 2015-09-30 20:17:52 +08:00
Sebastien Bourdeauducq 617c6ecb47 interconnect/stream: add multiplexer and demultiplexer 2015-09-30 19:43:51 +08:00
Sebastien Bourdeauducq 6c01f80fc5 genlib/fifo: add missing imports 2015-09-30 18:58:46 +08:00
Sebastien Bourdeauducq 0c1e1c9769 test/fifo: do not use Record 2015-09-30 17:06:31 +08:00
Sebastien Bourdeauducq b3d5d1628c interconnect/stream: remove param, do not depend on FIFO Record support 2015-09-30 16:40:34 +08:00
Sebastien Bourdeauducq 1b8f313d40 lasmicon: do not depend on FIFO Record support 2015-09-30 16:40:04 +08:00
Sebastien Bourdeauducq 4451bb20e5 genlib/fifo: remove Record support 2015-09-30 16:39:33 +08:00
Sebastien Bourdeauducq c36029fa61 command line options support, CSR CSV, all targets building 2015-09-29 18:14:54 +08:00
Sebastien Bourdeauducq e1927b7cbb flterm: cleanup 2015-09-29 18:14:19 +08:00
Sebastien Bourdeauducq 48b6733c33 cores/gpio: fix import 2015-09-29 18:13:59 +08:00
Sebastien Bourdeauducq 913558ab19 build: stop at the first failed Quartus command 2015-09-29 15:53:18 +08:00
Sebastien Bourdeauducq 5e45b6ced6 build: add missing import for Lattice Diamond 2015-09-29 15:44:57 +08:00
Sebastien Bourdeauducq 6d2d70d879 fhdl/FullMemoryWE: fix clocking 2015-09-29 13:12:27 +08:00
Sebastien Bourdeauducq b4c5ffc1ba fhdl: typecheck ClockSignal and ResetSignal arguments 2015-09-29 13:11:40 +08:00
Sebastien Bourdeauducq dd7dfb0d5e soc_core: simplify settings (assume CPU and CSR present) 2015-09-29 10:19:42 +08:00
Sebastien Bourdeauducq b1a90053f5 minor fixes 2015-09-29 10:19:00 +08:00
Sebastien Bourdeauducq 8e860e3aba Merge branch 'master' of github.com:m-labs/misoc 2015-09-28 20:40:37 +08:00
Sebastien Bourdeauducq 75d927e080 Revert "Sort constants in csr generation." 
This reverts commit d628c147ec.
 2015-09-28 20:40:31 +08:00
Sebastien Bourdeauducq 7c9a7ee757 build: cleanup 2015-09-28 20:34:35 +08:00
Sebastien Bourdeauducq 523377efbe basic out-of-tree build support (OK on PPro) 2015-09-28 20:33:37 +08:00
whitequark bd7748299b Fix typo. 2015-09-28 12:38:58 +03:00
Sebastien Bourdeauducq e92d00f767 move software into misoc 2015-09-28 15:30:19 +08:00
Tim 'mithro' Ansell 27a0e16fea Sort constants in csr generation. 
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.

With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
 CSR=software/include/generated/csr.h
 for i in 1 2 3 4 5 6; do
   rm -f $CSR; python make.py build-headers
   cp $CSR $CSR.$i
 done
 md5sum $CSR.*
```
 2015-09-27 11:05:54 +08:00
Tim 'mithro' Ansell d628c147ec Sort constants in csr generation. 
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.

With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
 CSR=software/include/generated/csr.h
 for i in 1 2 3 4 5 6; do
   rm -f $CSR; python make.py build-headers
   cp $CSR $CSR.$i
 done
 md5sum $CSR.*
```
 2015-09-27 11:04:28 +08:00
Sebastien Bourdeauducq 4fe0f6017c Revert "Use shutil rather then rm -rf command." 
This reverts commit d8fd4fe725.
 2015-09-26 21:55:11 +08:00
Sebastien Bourdeauducq a186bfe0f3 Revert "Use shutil rather then rm -rf command." 
This reverts commit d8fd4fe725.
 2015-09-26 21:54:19 +08:00
Sebastien Bourdeauducq 27b2383607 sdram working on PPro 2015-09-26 21:51:22 +08:00
Sebastien Bourdeauducq 09003a55e1 fhdl/specials/Tristate: handle i=None 2015-09-26 21:49:12 +08:00
Sebastien Bourdeauducq e136352e8f fhdl/structure: relax type requirements for Array elements 2015-09-26 21:47:33 +08:00
Sebastien Bourdeauducq 67133f3542 replace flen with len 2015-09-26 18:50:11 +08:00
Sebastien Bourdeauducq 808cf06add fhdl: replace flen with len 2015-09-26 18:45:10 +08:00
Sebastien Bourdeauducq fa1e8cd822 wrap expressions in Specials 2015-09-26 16:45:13 +08:00
Sebastien Bourdeauducq da425d1bcb add stream, fix CPUs and more imports. simple target boots on ppro. 2015-09-26 16:44:21 +08:00
Sebastien Bourdeauducq 8f42b6f352 fhdl: introduce wrap function 2015-09-26 15:36:28 +08:00
Sebastien Bourdeauducq 67903494bf fhdl: export DUID 2015-09-26 13:46:57 +08:00
Sebastien Bourdeauducq 75ef2f9004 fix most imports 2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq f69674e89c interconnect: add bus/bank components from Migen 2015-09-24 20:48:18 +08:00
Sebastien Bourdeauducq af88a7a3f9 setup: simpler version check, beta status 2015-09-24 16:08:39 +08:00
Sebastien Bourdeauducq ecdc4101b4 lasmicon: enable refresh at all times 2015-09-24 16:01:08 +08:00
Sebastien Bourdeauducq 9b08b037e4 break down sdram, improve consistency of core names 2015-09-24 15:59:55 +08:00