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9499 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou f06ef5205a soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor 2023-10-30 11:13:40 +01:00
Gwenhael Goavec-Merou 9374196974 soc/cores/uart: allows 64bits in Stream2Wishbone 2023-10-30 11:03:16 +01:00
Florent Kermarrec b5a9106f56 cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame. 2023-10-27 18:09:03 +02:00
enjoy-digital 5842ad7d14
Merge pull request #1818 from Dolu1990/nax-smp 
core/naxriscv update to main branch
 2023-10-27 16:32:28 +02:00
Dolu1990 5e482d641c core/naxriscv switch to main branch, and implement a reset controller internaly 2023-10-27 16:06:07 +02:00
Florent Kermarrec d021564fca interconnect/wishbone: Revert SRAM to Module, needs to be investigated. 2023-10-27 15:24:57 +02:00
enjoy-digital ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue 
test_csr: test cases to demonstrate a CSRStatus() issue
 2023-10-27 12:52:25 +02:00
Florent Kermarrec c44b906d9f interconnect/stream: Revert Convert to Module, needs to be investigated. 2023-10-27 12:33:37 +02:00
Florent Kermarrec 856d7452b3 gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains. 2023-10-27 12:26:54 +02:00
Florent Kermarrec fa629b782f CHANGES: Update. 2023-10-27 11:40:31 +02:00
enjoy-digital e55cf0f6d9
Merge pull request #1804 from zeldin/ecp5_pll_phase 
cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
 2023-10-27 11:37:50 +02:00
Florent Kermarrec 63159aa187 soc/cores: Minor cosmetic changes. 2023-10-27 11:29:38 +02:00
Florent Kermarrec 48f27707d1 soc/cores: Make sure all Modules are switched to LiteXModule. 2023-10-27 11:16:55 +02:00
Florent Kermarrec a2820cba96 interconnect/packet: Switch to LiteXModule. 2023-10-27 11:07:31 +02:00
Florent Kermarrec fa521f5c89 interconnect/wishbone: Switch to LiteXModule. 2023-10-27 11:05:37 +02:00
Florent Kermarrec 9ccac7f7e0 interconnect/stream: Switch to LiteXModule. 2023-10-27 11:03:33 +02:00
Florent Kermarrec 002aad7a43 soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls. 2023-10-27 10:55:13 +02:00
enjoy-digital cd3265b16c
Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addressing 
Add wishbone word/byte addressing.
 2023-10-27 10:12:28 +02:00
Andrew Dennison 203726bc03 test_csr: test cases for issue 
'status' reads as 0 in simulation when CSRStatus has fields.
 2023-10-27 13:05:51 +11:00
Florent Kermarrec 6e928efe82 cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting. 2023-10-26 17:50:39 +02:00
Florent Kermarrec 75752b4bff cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces. 2023-10-26 17:40:16 +02:00
Florent Kermarrec 7dc11e586b soc/add_adapter: Add initial addressing conversion between byte/word addressed. 2023-10-26 17:25:30 +02:00
Florent Kermarrec b19b7ed001 axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed. 2023-10-26 17:24:37 +02:00
Florent Kermarrec dde9605a5d csr_bus: Add addressing property. 2023-10-26 17:23:31 +02:00
Florent Kermarrec c5d869447a ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed. 2023-10-26 17:23:12 +02:00
Florent Kermarrec 4524262f64 axi/axi_lite: Add addressing parameters and assert on byte. 
Useful to have similar properties than Wishbone.
 2023-10-26 17:18:38 +02:00
Florent Kermarrec d6f7652b68 axi/axi_full: Add addressing parameters and assert on byte. 
Useful to have similar properties than Wishbone.
 2023-10-26 17:18:23 +02:00
Florent Kermarrec a4539c3dae interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing). 2023-10-26 17:16:59 +02:00
enjoy-digital 7006b49a39
Merge pull request #1812 from trabucayre/efinix_ti60f100_spiflash 
build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support
 2023-10-25 17:47:28 +02:00
Gwenhael Goavec-Merou ba2913f137 build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
 2023-10-25 17:05:24 +02:00
Florent Kermarrec 69dc666177 CHANGES: Update. 2023-10-25 16:01:45 +02:00
enjoy-digital cdeb4412f8
Merge pull request #1808 from hansfbaier/master 
Xilinx: Initial openxc7 toolchain support
 2023-10-24 08:41:12 +02:00
Hans Baier f3f46e8cf1 openxc7 toolchain: auto generate chipdb, if missing 2023-10-24 12:01:35 +07:00
Hans Baier 8d0f08a57e fix syntax errors 2023-10-24 08:52:49 +07:00
Hans Baier 468375b119 xilinx platform: add more ignored constraints for yosys+nextpnr 2023-10-24 08:39:01 +07:00
enjoy-digital 02b16f1f26
Merge pull request #1810 from trabucayre/etherbone_expose_params 
soc/integration/soc: expose interface,endianness and xx_cdc_xx to target (required for hybrid etherbone)
 2023-10-23 18:41:52 +02:00
Gwenhael Goavec-Merou bf3286f564 soc/integration/soc: expose interface and endianness to target (required for hybrid etherbone) 2023-10-23 18:41:00 +02:00
Florent Kermarrec 5a217528a4 build/generic_platform: Fix jtag_support typo. 2023-10-23 17:29:12 +02:00
Florent Kermarrec 86cf24023d soc/build: Minimize changes added by #1809 and review. 2023-10-23 16:41:03 +02:00
enjoy-digital ad98c7c630
Merge pull request #1809 from trabucayre/jtagbone_uartbone_parser 
soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone
 2023-10-23 16:03:42 +02:00
Gwenhael Goavec-Merou 745e584c60 soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone 
- `--with-jtagbone` and `--with-uartbone` are now integrated in SoCCore
  arguments. This class also handle `add_jtagbone` and `add_uartbone`
- when a target try to add one of this option a warning is displayed and
  insertion is bypassed
- `crossover+uartbone` is deprecated -> `--uart-name=crossover
  --with-uartbone`
- jtag capability ((un)supported) is now handled at platform level
 2023-10-23 11:21:19 +02:00
Hans Baier a833193cd3 Xilinx: Initial openxc7 toolchain support 2023-10-23 11:43:02 +07:00
Marcus Comstedt 6636560c41 cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output 2023-10-21 11:29:08 +02:00
Gwenhael Goavec-Merou 7e6418900a build/openocd: adding Efinix Titanium support 2023-10-17 17:37:34 +02:00
Gwenhael Goavec-Merou aad8311260 soc/cores/jtag: adding Efinix JTAG support in JTAGPHY 2023-10-17 17:37:13 +02:00
Gwenhael Goavec-Merou d95d5bdce9 build/efinix/ifacewriter, soc/cores/ram/efinix_hyperram: adding F100 internal HyperRAM support 2023-10-17 13:19:22 +02:00
Gwenhael Goavec-Merou 6f02a7f508 build/efinix/ifacewriter: adding PHASE_SHIFT_xx and CLKOUTx_DYNPHASE_EN 2023-10-17 13:17:53 +02:00
Gwenhael Goavec-Merou cd439da18e soc/cores/clock/efinix: allows dyn_phase_shift configuration 2023-10-17 13:17:31 +02:00
Gwenhael Goavec-Merou 5d7e9c94a6 build/efinix/dbparser: workaround for Ti60F100S3F2 with only 3 PLLs 2023-10-17 13:17:12 +02:00
Florent Kermarrec e499dd84b5 build/openfpgaloader: Add unprotect_flash capability. 2023-10-13 13:14:18 +02:00