enjoy-digital
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
Florent Kermarrec
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
Ilia Sergachev
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt
2d70220b80
bios: Fix warning on 64-bit
...
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
rprinz08
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
Florent Kermarrec
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
Florent Kermarrec
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
Florent Kermarrec
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
Florent Kermarrec
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
Florent Kermarrec
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
Dave Marples
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
Dave Marples
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
Florent Kermarrec
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
Florent Kermarrec
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
Florent Kermarrec
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
Gabriel Somlo
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
shuffle2
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
Florent Kermarrec
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
Florent Kermarrec
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
Florent Kermarrec
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
Florent Kermarrec
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
Florent Kermarrec
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
Florent Kermarrec
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
Florent Kermarrec
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
Florent Kermarrec
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
enjoy-digital
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
enjoy-digital
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
Sadullah Canakci
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
sadullah
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
sadullah
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
sadullah
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
sadullah
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
sadullah
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
Sadullah Canakci
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
enjoy-digital
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
Florent Kermarrec
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
Gabriel Somlo
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
Florent Kermarrec
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
Franck Jullien
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
Franck Jullien
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
Franck Jullien
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
Franck Jullien
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
Franck Jullien
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
Florent Kermarrec
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
Florent Kermarrec
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
Florent Kermarrec
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
Florent Kermarrec
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
Florent Kermarrec
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
David Shah
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
Ilya Epifanov
83f4dcb2c6
Added imac config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
Jakub Cebulski
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
Florent Kermarrec
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
Florent Kermarrec
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
enjoy-digital
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
Franck Jullien
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
enjoy-digital
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
Florent Kermarrec
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
Florent Kermarrec
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
Florent Kermarrec
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
Florent Kermarrec
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
Florent Kermarrec
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
Florent Kermarrec
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
enjoy-digital
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
Jakub Cebulski
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
Jędrzej Boczar
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
Florent Kermarrec
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
Florent Kermarrec
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
Florent Kermarrec
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
Mateusz Holenko
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
Florent Kermarrec
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
Florent Kermarrec
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
Tim 'mithro' Ansell
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
Florent Kermarrec
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
David Sawatzke
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
Florent Kermarrec
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
Florent Kermarrec
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
Florent Kermarrec
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
Florent Kermarrec
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
Florent Kermarrec
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
Florent Kermarrec
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
Florent Kermarrec
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
