8c73afea91
Merge pull request #1823 from trabucayre/cpuNone_config
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litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width
2023-10-30 18:42:54 +01:00
16133359d6
soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)
2023-10-30 18:13:46 +01:00
eedebd8adb
litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width
2023-10-30 17:17:16 +01:00
4b9601bdab
Merge pull request #1822 from trabucayre/rework_tools
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tools: litex_server, litex_client and remote: don't hardcode bus address
2023-10-30 17:13:46 +01:00
a2c39a7bbf
tools: litex_server, litex_client and remote: don't hardcode bus address
2023-10-30 16:20:31 +01:00
5efdbd9c20
Merge pull request #1821 from trabucayre/uartbone_add_width
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UARTBone addr width
2023-10-30 15:03:37 +01:00
321254cc38
soc/integration/soc: pass bus.address_width to UARTBone constructor
2023-10-30 11:14:30 +01:00
f06ef5205a
soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor
2023-10-30 11:13:40 +01:00
9374196974
soc/cores/uart: allows 64bits in Stream2Wishbone
2023-10-30 11:03:16 +01:00
b5a9106f56
cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame.
2023-10-27 18:09:03 +02:00
5842ad7d14
Merge pull request #1818 from Dolu1990/nax-smp
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core/naxriscv update to main branch
2023-10-27 16:32:28 +02:00
5e482d641c
core/naxriscv switch to main branch, and implement a reset controller internaly
2023-10-27 16:06:07 +02:00
d021564fca
interconnect/wishbone: Revert SRAM to Module, needs to be investigated.
2023-10-27 15:24:57 +02:00
ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue
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test_csr: test cases to demonstrate a CSRStatus() issue
2023-10-27 12:52:25 +02:00
c44b906d9f
interconnect/stream: Revert Convert to Module, needs to be investigated.
2023-10-27 12:33:37 +02:00
856d7452b3
gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.
2023-10-27 12:26:54 +02:00
fa629b782f
CHANGES: Update.
2023-10-27 11:40:31 +02:00
e55cf0f6d9
Merge pull request #1804 from zeldin/ecp5_pll_phase
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cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
2023-10-27 11:37:50 +02:00
63159aa187
soc/cores: Minor cosmetic changes.
2023-10-27 11:29:38 +02:00
48f27707d1
soc/cores: Make sure all Modules are switched to LiteXModule.
2023-10-27 11:16:55 +02:00
a2820cba96
interconnect/packet: Switch to LiteXModule.
2023-10-27 11:07:31 +02:00
fa521f5c89
interconnect/wishbone: Switch to LiteXModule.
2023-10-27 11:05:37 +02:00
9ccac7f7e0
interconnect/stream: Switch to LiteXModule.
2023-10-27 11:03:33 +02:00
002aad7a43
soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.
2023-10-27 10:55:13 +02:00
cd3265b16c
Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addressing
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Add wishbone word/byte addressing.
2023-10-27 10:12:28 +02:00
203726bc03
test_csr: test cases for issue
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'status' reads as 0 in simulation when CSRStatus has fields.
2023-10-27 13:05:51 +11:00
6e928efe82
cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting.
2023-10-26 17:50:39 +02:00
75752b4bff
cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces.
2023-10-26 17:40:16 +02:00
7dc11e586b
soc/add_adapter: Add initial addressing conversion between byte/word addressed.
2023-10-26 17:25:30 +02:00
b19b7ed001
axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed.
2023-10-26 17:24:37 +02:00
dde9605a5d
csr_bus: Add addressing property.
2023-10-26 17:23:31 +02:00
c5d869447a
ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed.
2023-10-26 17:23:12 +02:00
4524262f64
axi/axi_lite: Add addressing parameters and assert on byte.
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Useful to have similar properties than Wishbone.
2023-10-26 17:18:38 +02:00
d6f7652b68
axi/axi_full: Add addressing parameters and assert on byte.
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Useful to have similar properties than Wishbone.
2023-10-26 17:18:23 +02:00
a4539c3dae
interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing).
2023-10-26 17:16:59 +02:00
7006b49a39
Merge pull request #1812 from trabucayre/efinix_ti60f100_spiflash
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build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support
2023-10-25 17:47:28 +02:00
ba2913f137
build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
2023-10-25 17:05:24 +02:00
69dc666177
CHANGES: Update.
2023-10-25 16:01:45 +02:00
cdeb4412f8
Merge pull request #1808 from hansfbaier/master
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Xilinx: Initial openxc7 toolchain support
2023-10-24 08:41:12 +02:00
f3f46e8cf1
openxc7 toolchain: auto generate chipdb, if missing
2023-10-24 12:01:35 +07:00
8d0f08a57e
fix syntax errors
2023-10-24 08:52:49 +07:00
468375b119
xilinx platform: add more ignored constraints for yosys+nextpnr
2023-10-24 08:39:01 +07:00
02b16f1f26
Merge pull request #1810 from trabucayre/etherbone_expose_params
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soc/integration/soc: expose interface,endianness and xx_cdc_xx to target (required for hybrid etherbone)
2023-10-23 18:41:52 +02:00
bf3286f564
soc/integration/soc: expose interface and endianness to target (required for hybrid etherbone)
2023-10-23 18:41:00 +02:00
5a217528a4
build/generic_platform: Fix jtag_support typo.
2023-10-23 17:29:12 +02:00
86cf24023d
soc/build: Minimize changes added by #1809 and review.
2023-10-23 16:41:03 +02:00
ad98c7c630
Merge pull request #1809 from trabucayre/jtagbone_uartbone_parser
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soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone
2023-10-23 16:03:42 +02:00
745e584c60
soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone
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- `--with-jtagbone` and `--with-uartbone` are now integrated in SoCCore
arguments. This class also handle `add_jtagbone` and `add_uartbone`
- when a target try to add one of this option a warning is displayed and
insertion is bypassed
- `crossover+uartbone` is deprecated -> `--uart-name=crossover
--with-uartbone`
- jtag capability ((un)supported) is now handled at platform level
2023-10-23 11:21:19 +02:00
a833193cd3
Xilinx: Initial openxc7 toolchain support
2023-10-23 11:43:02 +07:00
6636560c41
cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
2023-10-21 11:29:08 +02:00
enjoy-digital
Gwenhael Goavec-Merou
Dolu1990
Andrew Dennison
Gwenhael Goavec-Merou
Hans Baier
Marcus Comstedt