48312890e5
boards/platforms/kc705: use vivado as default programmer
2019-01-21 10:40:32 +01:00
1b23890e0d
soc/cores/clock: allow ClockSignal to be used for clkin
2019-01-16 22:05:52 +01:00
387ee04130
build/sim/core: fix coverage
2019-01-11 15:01:58 +01:00
482abf9b43
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
2019-01-11 13:51:15 +01:00
9c5f654773
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
2019-01-11 13:39:09 +01:00
f132012de1
build/sim: disable Warning-WIDTH
2019-01-10 16:03:09 +01:00
7c67bac723
soc/cores/cpu/vexriscv: set default variant to None in add_sources
2019-01-09 10:28:24 +01:00
648015d78e
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
2019-01-09 09:19:40 +01:00
2b5a6f1058
targets/kcu105: use USMMCM
2019-01-08 14:14:28 +01:00
86e19e6232
targets: pass speedgrade to S7PLL/S7MMCM
2019-01-08 13:50:12 +01:00
2581a00380
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
2019-01-08 13:21:53 +01:00
68e1dfca28
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
...
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
041bf41226
soc/integration/cpu_interface: generate name for Memories in get_csr_header
2019-01-05 10:57:37 +01:00
9f5d0cef6b
utils/litex_server: allow specify uart_baudrate as float
2019-01-03 10:38:14 +01:00
2c43f6f7dc
targets/ulx3s: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:58:28 +01:00
5ef4d09caa
targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:39:20 +01:00
9c801fbe50
soc/cores/clock/ECP5PLL: add basic phase support
2018-12-28 15:03:12 +01:00
a7b5b9d212
litex_sim: simplify, change sdram module and enable sdram refresh.
2018-12-27 20:36:50 +01:00
a7378a721c
.gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists.
2018-12-23 19:47:48 +01:00
2deffd8c8a
build/sim/verilator: compile sim just before running and not when building.
2018-12-21 09:59:34 +01:00
291843ee76
Merge pull request #144 from mithro/nextpnr-migen-update
...
Integrate latest migen changes for lattice/icestorm.
2018-12-20 11:35:42 -08:00
53731b792b
Integrate latest migen changes for lattice/icestorm.
...
Integrated up to 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a.
2018-12-20 11:33:19 -08:00
180912a7a3
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
2018-12-20 10:38:40 +01:00
b6c98cab0d
platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4)
2018-12-19 11:33:32 +01:00
ebe0d567f8
bios/sdram: only show read delays when they are valid.
2018-12-19 11:19:47 +01:00
67a2590235
bios/sdram: reduce write leveling scan range
2018-12-19 11:18:19 +01:00
fe5cef4294
soc/cores/clock: remove return on S7PLL.create_clkout
2018-12-19 09:14:26 +01:00
eda1a83ea9
platforms/kcu105: set internal vref on ddr4 banks
2018-12-18 21:38:23 +01:00
a27b5a3be1
update Ultrascale DDRPHY
2018-12-18 11:25:21 +01:00
1c1c1bd122
Merge pull request #141 from mithro/xst-fix
...
Fix `-vlgincdir` for xst.
2018-12-17 21:24:15 -08:00
8b2abc7e89
Fix `-vlgincdir` for xst.
...
The command line is of the form;
```
-vlgincdir {"path1" "path2"}
```
Fixes the following error;
```
WARNING:Xst:3164 - Option "-vlgincdir" found multiple times in the command line. Only the first occurence is considered.
```
2018-12-17 21:11:14 -08:00
f8f3683aaa
bios/sdram: reduce scans verbosity on ultrascale
2018-12-17 16:00:44 +01:00
efce434aa9
bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
2018-12-17 11:43:21 +01:00
0ade06c0f0
Merge pull request #138 from mithro/mainram-hack
...
Hack to fix #136 .
2018-12-16 14:42:36 -08:00
22d454efcd
Hack to fix #136 .
2018-12-16 14:40:10 -08:00
fa6fef1e15
Merge pull request #135 from mithro/icestorm-ice40up5k
...
Add uwg30 package and up3k part.
2018-12-16 14:04:19 -08:00
9481781d1c
Add uwg30 package and up3k part.
2018-12-16 14:03:29 -08:00
e9f1049200
soc/cores/cpu/vexriscv: add add_debug method for debug variants
2018-12-12 10:01:49 +01:00
35155e5172
soc/cores/cpu/vexriscv: add support for the new variants.
2018-12-12 09:39:30 +01:00
2ace45e6f8
soc/cores/cpu/vexriscv: update submodule
2018-12-12 09:38:53 +01:00
6d6c2b4c45
soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)
2018-12-12 09:38:10 +01:00
584fd51c01
build/sim/verilator: add support for plaform.sources, some cleanup
2018-12-12 09:37:24 +01:00
c9915f89ce
build/microsemi/libero_soc: fix typos
2018-12-12 09:34:43 +01:00
99578bc68c
gen/sim/core: add args support on Display
2018-12-09 09:46:10 +01:00
fa260f5b42
gen/fhdl: add simulation Display, Finish support.
...
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
92a6169d2a
build/sim: add coverage parameter to enable code coverage
2018-12-09 08:10:50 +01:00
0c687bc29e
soc/interconnect/stream: add support for buffered async fifo
2018-12-08 01:24:08 +01:00
bf3b4eec34
gen: integrate migen changes
2018-12-04 21:06:51 +01:00
96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
Florent Kermarrec
Tim Ansell