181aeb4791
Add example of hamming generator and checker instances
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2015-04-10 16:15:55 +08:00
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
beeaefccea
move pytholite to separate repos
2015-03-14 22:48:03 +01:00
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
702d177c85
mibuild: get rid of Platform factory function, cleanup
2015-03-13 23:25:15 +01:00
e82531cdf8
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
b3faf5f0da
mibuild: better file organization (create directory for each vendor and move programmers in it)
2015-02-26 12:25:59 +01:00
c7eba8f4c4
remove crc since each crc is specific. It's probably better to adapt code for each case.
2015-02-14 03:01:12 -08:00
4542de2c11
genlib/fsm: add NextValue to replace reg/reg_next/ce pattern
2014-11-25 17:16:21 +08:00
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
e03091e7e2
add generic CRCEngine, CRC32, CRCInserter and CRCChecker
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CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
2014-09-26 11:42:10 +08:00
3d84a7a9de
cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic
2014-09-07 16:49:12 +08:00
7518a7b0c0
examples/dataflow: adapt to new simple MultiDiGraph implementation
2014-09-07 16:48:46 +08:00
8489604142
examples/dataflow/dma: fix simulation, run it for 100 cycles
2014-09-07 16:48:46 +08:00
7ad1028f8b
mibuild: use SimpleCRG instead of CRG_SE, remove period parameter for CRG_DS, clean up platforms
2014-06-20 17:29:29 +02:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
ad70d056a8
examples/sim/cordic_err: fix rms_err function name
2013-12-02 13:18:37 +01:00
b3c79738e1
examples/cordic/cordic_impl: do not fail if build dir does not exist
2013-12-02 13:03:26 +01:00
ab48316fcd
examples/cordic: scripted exploration of parameters space
2013-12-02 12:56:29 +01:00
9762546c95
genlib/cordic: cleanup, documentation, unittests
2013-12-02 12:56:24 +01:00
7e4024beb3
genlib/fsm: rename {entering,leaving} to after_{entering,leaving}, add before_{entering,leaving}
2013-11-21 23:30:24 +01:00
4fb3e970b1
genlib/fsm: add entering/ongoing/leaving methods
2013-09-06 14:51:18 +02:00
87a68ecd57
examples/basic/namer: cleanup
2013-09-04 17:20:40 +02:00
b96eb339af
fhdl: compact Instance syntax
2013-07-25 20:34:19 +02:00
fcd48dafec
examples/two_dividers: demonstrate InsertCE and InsertReset decorators
2013-07-25 17:56:55 +02:00
83e2b0243d
examples: remove direct uses of Fragment
2013-07-24 18:47:25 +02:00
1d33c61308
examples/sim/abstract_transactions_lasmi: check data
2013-07-10 19:11:02 +02:00
4096a785f9
examples/pytholite/basic: demonstrate generator arguments
2013-07-03 16:35:24 +02:00
6420b56908
examples/complex: do not use variable
2013-06-30 19:27:01 +02:00
a255296171
support re-slicing and non-unit step size
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* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
2013-06-30 14:03:34 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
9f560cb758
examples/sim: add LASMI demo
2013-06-09 23:36:51 +02:00
2948f6a16a
examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI
2013-06-09 14:17:30 +02:00
bac62a32a9
Make memory ports part of specials
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This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
746e452838
actorlib/dma_asmi: support for writes
2013-04-28 18:06:36 +02:00
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
b38818eb17
examples/sim/fir: convert to new API
2013-03-19 11:46:27 +01:00
af4eb02551
examples/basic/arrays: demonstrate lowering of Array in Instance expression
2013-03-18 18:37:23 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
Guy Hutchison
Sebastien Bourdeauducq
Robert Jordens
Florent Kermarrec
Sebastien Bourdeauducq