Florent Kermarrec
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
Florent Kermarrec
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
Florent Kermarrec
ef1c778446
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
2018-07-10 13:29:32 +02:00
Florent Kermarrec
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
Sergiusz Bazanski
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
Florent Kermarrec
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
Florent Kermarrec
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
Florent Kermarrec
db6c88bbef
soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases)
2017-10-12 11:30:56 +02:00
Florent Kermarrec
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
Florent Kermarrec
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
Florent Kermarrec
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
Florent Kermarrec
5efd6a8412
soc/interconnect/stream_packet.py: make error payload optional on Packetizer
2017-03-28 12:21:54 +02:00
Florent Kermarrec
ff31959aea
merge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-13 03:55:00 +01:00
Florent Kermarrec
30f7dd69bd
soc/interconnect/stream/: add busy signal to PipelinedActor
2017-01-10 02:18:21 +01:00
Florent Kermarrec
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
Florent Kermarrec
e6681bbb9c
soc/interconnect/wishbone: add FlipFlop (should be removed)
2016-04-25 19:14:20 +02:00
Florent Kermarrec
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
Florent Kermarrec
3d222d9e63
soc/interconnect/dma_lasmi: change endpoint names
2016-04-13 18:28:52 +02:00
Florent Kermarrec
b2eaf412c1
soc/interconnect/stream/PipelinedActor: add latency attribute
2016-04-07 12:10:32 +02:00
Florent Kermarrec
1d4f44e7db
soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores
2016-03-31 00:02:22 +02:00
Florent Kermarrec
9517b9b870
soc/interconnect/stream_sim: use passive generators and some cleanup
2016-03-23 01:04:33 +01:00
Florent Kermarrec
cf29ee0b91
soc/interconnect/stream_sim: adapt to new simulator
2016-03-21 19:56:43 +01:00
Florent Kermarrec
71a719be44
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 20:13:47 +01:00
Florent Kermarrec
9032665750
soc/interconnect/wishbonebridge: fix import
2016-03-16 19:34:50 +01:00
Florent Kermarrec
d7112efdba
soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now)
2016-03-16 19:33:29 +01:00
Florent Kermarrec
39aacf2df4
soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring
2016-03-16 19:33:00 +01:00
Florent Kermarrec
e0e2427795
soc: replace all Sink/Source with stream.Endpoint
2016-03-16 18:05:57 +01:00
Florent Kermarrec
c860581b86
soc/interconnect/stream: use new Converter/StrideConverter
2016-03-16 17:00:58 +01:00
Florent Kermarrec
8c272c1f6f
soc/interconnect/stream: fix missing param
2016-03-16 16:21:32 +01:00
Florent Kermarrec
cb47373383
soc/interconnect/stream: remove packetized parameter and use of sop
2016-03-16 11:54:28 +01:00
Florent Kermarrec
44a5b95281
soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter)
2016-03-15 15:52:57 +01:00
Florent Kermarrec
2218ece98a
soc/interconnect/stream: fix merge issue (missing params connect)
2016-02-01 00:08:27 +01:00
Florent Kermarrec
0498a31818
some cleanup
...
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
2015-12-27 13:09:58 +01:00
Florent Kermarrec
6ea65f957c
soc/interconnect/stream: expose Endpoint
2015-12-19 21:49:45 +01:00
Florent Kermarrec
f6aeb6e41a
soc/interconnect/stream: improve Pipeline to allow passing endpoints
2015-11-28 18:31:47 +01:00
Florent Kermarrec
d85d2b7b9b
soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
2015-11-27 20:14:01 +01:00
Florent Kermarrec
7298fff1e6
soc/interconnect/stream_packet: fix Counter removing
2015-11-24 20:30:53 +01:00
Florent Kermarrec
71483b8935
soc/tools: initialize wishbone remote control (for now only uart)
2015-11-17 01:05:52 +01:00
Florent Kermarrec
1f80bb9561
soc/interconnect/stream_packet: remove Counter
2015-11-16 16:53:23 +01:00
Florent Kermarrec
ec35290c45
soc/interconnect/wishbonebridge: remove Counter
2015-11-16 16:48:37 +01:00
Florent Kermarrec
2f52d364af
soc/interconnect/stream/SyncFIFO: expose fifo level
2015-11-16 16:11:31 +01:00
Florent Kermarrec
3a2e6117f4
soc/interconnect/stream: add Cast and others small fixes
2015-11-14 12:17:09 +01:00
Florent Kermarrec
16ba646b1b
add TODOs
2015-11-14 03:15:10 +01:00
Florent Kermarrec
032f5a9620
soc/interconnect: add stream_sim
2015-11-14 00:43:49 +01:00
Florent Kermarrec
ba959c832d
soc/interconnect: rename packet to stream_packet
2015-11-14 00:42:58 +01:00
Florent Kermarrec
fc3ffe87ac
for now use our fork of migen (to be able to simulate our designs)
2015-11-13 18:31:46 +01:00
Florent Kermarrec
7d6cee6751
soc/interconnect/stream: add BufferizeEndpoints
2015-11-12 18:54:15 +01:00
Florent Kermarrec
83427c87cd
soc/interconnect/stream: add Pipeline
2015-11-12 01:41:23 +01:00
Florent Kermarrec
81c6facca2
soc/interconnect/stream: reintroduce params
2015-11-12 01:12:15 +01:00
Florent Kermarrec
f6b30fcae2
soc/interconnect: add packet
2015-11-12 00:54:40 +01:00
Florent Kermarrec
525da89c7d
soc/interconnect: add wishbonebridge and uart bridge
2015-11-12 00:52:36 +01:00
Florent Kermarrec
89b189ce4a
soc/interconnect/stream: reintroduce PipelinedActor/Buffer
2015-11-12 00:51:32 +01:00
Florent Kermarrec
619cd8e695
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
2015-11-11 12:10:55 +01:00
Florent Kermarrec
3f43a49382
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
...
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
2015-11-10 16:51:51 +01:00
Florent Kermarrec
6a0f85dc42
litex: reorganize things, first work working version
2015-11-07 17:48:55 +01:00
