209 commits

Author	SHA1	Message	Date
Benjamin Herrenschmidt	f628ff6b47	WB2CSR: Use CSR address_width for the wishbone bus ... Currently, we create a wishbone interface with the default address width (30 bits) for the bridge. Instead, create an interface that has the same number of address bits as the CSR bus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2020-05-12 21:37:36 +10:00
Dave Marples	967e38bb57	Small fixups to address compiler warnings etc.	2020-05-07 09:26:46 +01:00
Florent Kermarrec	d44fe18bd9	stream/AsyncFIFO: add default depth (useful when used for CDC).	2020-04-14 17:35:19 +02:00
Florent Kermarrec	a67ab41835	interconnect/csr: add reset_less parameter. ... In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.	2020-04-06 13:15:08 +02:00
Florent Kermarrec	05b1b7787b	interconnect/csr, wishbone: use reset_less on datapath signals.	2020-04-06 13:11:50 +02:00
Florent Kermarrec	a35df4f7d1	stream: set reset_less to True on datapath signals. ... Reset is only required on control signals.	2020-04-06 11:33:49 +02:00
Karol Gugala	da580e31fd	Fix copyrights ... Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>	2020-03-05 17:44:10 +01:00
Florent Kermarrec	12a7528667	interconnect/stream/SyncFIFO: allow depth down to 0.	2020-02-28 21:54:02 +01:00
Florent Kermarrec	9e31bf357e	interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.	2020-02-28 16:33:18 +01:00
Florent Kermarrec	1e0e96f9a0	interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.	2020-02-28 16:25:09 +01:00
Florent Kermarrec	6be7e9c33d	interconnect/axi: set default data_width/address_width to 32-bit.	2020-02-28 13:20:01 +01:00
Florent Kermarrec	935e4effd2	interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)	2020-02-26 15:13:29 +01:00
Florent Kermarrec	0042a02807	interconnect/axi: remove bus_name on connect_to_pads	2020-02-24 13:24:32 +01:00
Florent Kermarrec	a3584147a5	litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.	2020-02-24 12:48:52 +01:00
Florent Kermarrec	d86db6f12b	litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.	2020-02-24 12:48:20 +01:00
Karol Gugala	79a14001b0	axi: add to_pads method ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2020-02-21 12:22:18 +01:00
Jan Kowalewski	e0bcb57d3d	wishbone: add extracting module signals to the top	2020-02-21 11:20:32 +01:00
Florent Kermarrec	9baa3ad5bb	soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)	2020-02-18 09:13:32 +01:00
Florent Kermarrec	0497f3ca71	soc/csr_bus: improve CSR paging genericity	2020-02-17 08:28:56 +01:00
Florent Kermarrec	67e8a042f8	integration/soc: add configurable CSR Paging	2020-02-16 12:32:05 +01:00
Florent Kermarrec	18a9d4ff2f	interconnect/stream: cleanup imports/idents	2020-02-14 08:08:19 +01:00
Florent Kermarrec	1feff1d7d5	soc: integrate CSR master/interconnect/collection and IRQ collection	2020-02-07 19:50:35 +01:00
Florent Kermarrec	3350d33f9c	wishbone/Cache: add reverse parameter	2020-01-31 19:31:33 +01:00
Florent Kermarrec	9d2894727e	inteconnect/stream: use PipeValid implementation for Buffer	2020-01-30 09:36:04 +01:00
Florent Kermarrec	1c88c0f896	inteconnect/stream: cleanup	2020-01-30 09:32:04 +01:00
Florent Kermarrec	f3f9808d1f	interconnect/stream: add PipeValid and PipeWait to cut timing paths.	2020-01-29 18:27:29 +01:00
Florent Kermarrec	a26853702c	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
Florent Kermarrec	fa22d6aa82	wishbone/Cache: avoid REFILL_WRTAG state to improve speed.	2020-01-10 14:25:07 +01:00
Gabriel Somlo	d087e2e0af	interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) ... Similarly to how CSRBank subregisters are aligned to the CPU word width (see commit f4770219f), ensure SRAM word_bits are also aligned to the CPU word width. Additionally, fix the MMPTR() macro to access CSR subregisters as CPU word (unsigned long) sized slices. This fixes the functionality of the 'ident' bios command on 64-bit CPUs (e.g., Rocket). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-01-03 16:36:42 -05:00
Florent Kermarrec	6de20f185a	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
Florent Kermarrec	04017519c8	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
Florent Kermarrec	1efb18f1ea	soc/interconnect/packet/Depacketizer: another simplifcation pass	2019-11-18 09:06:56 +01:00
Florent Kermarrec	af52203c00	soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state	2019-11-17 11:57:14 +01:00
Florent Kermarrec	8272a00d6e	soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last	2019-11-17 11:50:09 +01:00
Florent Kermarrec	6059712794	test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer	2019-11-16 14:39:18 +01:00
Florent Kermarrec	9642893371	test/test_packet: add randomness on valid input, fix corner-cases on Packetizer	2019-11-16 08:49:04 +01:00
enjoy-digital	888fd55bd8	Merge pull request #307 from sergachev/master ... change >512 B CSR memory exception to a warning	2019-11-15 18:17:35 +01:00
Florent Kermarrec	2f2cfc9951	soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))	2019-11-15 16:19:05 +01:00
Ilia Sergachev	444ae951e9	change >512 B CSR memory exception to a warning	2019-11-15 15:34:12 +01:00
Florent Kermarrec	31661e9e2d	soc/interconnect/packet: connect error/last_be only present on both sink and source	2019-11-15 14:57:31 +01:00
Florent Kermarrec	2946581e50	soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple ... To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.	2019-11-15 14:39:55 +01:00
Florent Kermarrec	86662b54d0	soc/interconnect/packet: update copyright	2019-11-15 11:25:38 +01:00
Vamsi K Vytla	5c19b133ac	soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer ... With high speed link (10gbps XGMII ethernet for example), stream data_width is generally > 8-bit which make header/data un-aligned on bytes boundaries. The change allows the Packetizer/Depacketizer to work on stream with a data_width > 8-bit.	2019-11-15 11:24:17 +01:00
Florent Kermarrec	9c3c43c94a	interconnect/csr_bus/SRAM: add mem_size check ... Memory size is limited to 512 bytes: - CSR region size is 0x800 (4096) - default csr_data_width is 8 maximum size = 4096/8 = 512 bytes.	2019-11-01 11:33:50 +01:00
Florent Kermarrec	29e51f5e97	interconnect/wishbone: fix Converter case when buses are identical	2019-10-11 21:49:11 +02:00
Florent Kermarrec	ca81cc209b	soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)	2019-10-11 09:01:08 +02:00
Florent Kermarrec	03faf06c82	soc/interconnect/axi: re-align to improve readability	2019-10-11 08:41:05 +02:00
Florent Kermarrec	427d7af767	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00
Florent Kermarrec	59bf04d965	soc/interconnect/stream: add separators, mode Actor modules just after Endpoint	2019-09-30 23:33:25 +02:00
Florent Kermarrec	1425a68d9e	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) ... Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.	2019-09-24 17:55:29 +02:00
Florent Kermarrec	ffd2be2ba0	csr: add we signal to CSR, CSRStatus ... Doing actions on register read is generally not a good design practice (it's better to do separate register write to trigger actions) but in some very specific cases being able to know that register has been read can solve cases that are difficult to do with the recommended practives and that can justify doing an exception. This commit add a we signal to CSR, CSRStatus and this allow the logic to know when the CSR, CSRStatus is read.	2019-09-24 17:51:06 +02:00
Sean Cross	60d8572c3e	csr_eventmanager: add name and description args ... Add `name` and `description` as optional arguments to the various EventSource types. These default to `None`, so this should be a backwards-compatible change. Use the same trick as CSRs, where we default the `name` to be the instantiated object name as read from the Migen `get_obj_var_name()` call. Signed-off-by: Sean Cross <sean@xobs.io>	2019-09-19 17:23:03 +08:00
Florent Kermarrec	99ed0877ac	csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)	2019-09-18 10:47:54 +02:00
Florent Kermarrec	cca0478a5e	soc/cores/spi: use new CSRField (no functional change)	2019-09-16 17:02:55 +02:00
Florent Kermarrec	9bda614a3e	csr: update copyrights	2019-09-16 08:49:00 +02:00
Florent Kermarrec	29134cc659	csr: more documentation	2019-09-16 08:45:29 +02:00
Florent Kermarrec	74e756aa30	csr/CSRStorage: remove storage_full (was only needed by alignment_bits)	2019-09-16 08:38:26 +02:00
Florent Kermarrec	5dc440e80d	csr: use IntEnum for CSRAccess	2019-09-16 08:36:25 +02:00
Florent Kermarrec	d2646f138e	csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful	2019-09-15 19:47:48 +02:00
Florent Kermarrec	8e14694eb5	csr/fields: document, add separators, 100 characters per line	2019-09-15 19:11:25 +02:00
Florent Kermarrec	4e84729cf9	csr/fields: add access parameter	2019-09-14 22:16:18 +02:00
Florent Kermarrec	23b01f8f02	csr/fields: add pulse mode support	2019-09-14 21:49:34 +02:00
Florent Kermarrec	8c080e5fb6	soc/interconnect/csr: add initial field support	2019-09-13 20:01:31 +02:00
Florent Kermarrec	19f58dd971	interconnect/wishbone: add FlipFlop to allow UpConverter to be used ... Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up	2019-09-09 11:47:36 +02:00
Florent Kermarrec	67a09aef05	soc/interconnect/stream: add Monitor module ... Generic module to monitor endpoints activity: tokens/overflows/underflows that can be plugged on a endpoint. Can be useful for various purpose: - endpoint bandwidth calculation. - underflows/overflows detection. - etc...	2019-09-05 11:54:14 +02:00
chmousset	db4c609a33	[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat	2019-08-14 11:30:39 +02:00
Florent Kermarrec	a9fe2788a2	wishbone/SRAM: make read_only emited verilog code compatible with all tools ... Quartus was not able to implement ROM correctly, see #228	2019-08-05 09:08:56 +02:00
Florent Kermarrec	f4770219fa	soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs	2019-07-08 10:20:51 +02:00
Florent Kermarrec	4ee9c53f18	csr: add assert to ensure CSR size < busword (thanks tweakoz)	2019-07-03 13:44:15 +02:00
Florent Kermarrec	daa4307d9e	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
Florent Kermarrec	08a811b1a5	soc/interconnect/gearbox: add msb_first/lsb_first order	2019-05-29 10:25:25 +02:00
Florent Kermarrec	5109511259	soc/interconnect/axi: add round/robin arbitration between writes/reads	2019-05-25 10:02:31 +02:00
Florent Kermarrec	67159349d6	soc/interconnect: remove axi_lite ... axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.	2019-05-11 09:12:20 +02:00
Florent Kermarrec	0714816f31	soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone	2019-05-03 11:59:06 +02:00
Florent Kermarrec	c6d0d23445	soc/interconnect/axi: add AXI Lite definition	2019-05-03 09:43:12 +02:00
Florent Kermarrec	9fab4752c4	soc/interconnect/axi: add comment on axi signas that are present but not used	2019-05-03 09:30:59 +02:00
Florent Kermarrec	6cf1ff091c	soc/interconnect/axi: connect axi.ar/aw when selecting write or read	2019-05-02 09:58:55 +02:00
Florent Kermarrec	6affc56a09	soc/interconnect/axi: wishbone address shift is not always 2, make it generic	2019-05-02 09:35:07 +02:00
Florent Kermarrec	698bc88296	soc/interconnect/wishbone: allow setting adr_width (default to 30)	2019-05-02 09:34:30 +02:00
Florent Kermarrec	4dccb8a9eb	soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent	2019-05-01 12:59:04 +02:00
Florent Kermarrec	5c1d980540	soc/interconnect/axi: add burst support to AXI2Wishbone	2019-04-29 16:49:20 +02:00
Florent Kermarrec	6de2713524	soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize	2019-04-29 14:02:05 +02:00
Florent Kermarrec	9cbed91b3e	soc/interconnect/axi: add AXIBurst2Beat ... Converts AXI bursts commands to AXI beats.	2019-04-19 12:13:16 +02:00
Florent Kermarrec	5a8115d9e1	soc/interconnect/avalon: add description	2019-04-19 11:43:15 +02:00
Florent Kermarrec	a92e90b215	soc/interconnect: add avalon with converters to/from native streams	2019-04-18 18:42:29 +02:00
Florent Kermarrec	b15fd9d834	interconnect/axi: add missing axi signals	2019-04-01 10:23:25 +02:00
Gabriel L. Somlo	449632e430	soc/interconnect/axi: data/address length cleanup ... Instead of hard-coding data and address width to 32, assert that the AXI and Wishbone interfaces have *matching* address and data widths.	2019-03-27 16:52:52 -04:00
Florent Kermarrec	552b0243b3	soc/interconnect/axi: remove dead code (thanks gsomlo)	2019-03-27 21:15:14 +01:00
Florent Kermarrec	3c527dcbdf	soc/interconnect: add initial axi code with bus definition and AXI2Wishbone	2019-02-27 22:26:57 +01:00
Florent Kermarrec	ed2578799b	test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)	2019-02-27 22:24:56 +01:00
Florent Kermarrec	4aa07f2ae9	soc/interconnect: rename axi to axi_lite	2019-02-27 22:11:09 +01:00
Florent Kermarrec	57b8bdd530	soc/integration/soc_core: allow disabling wishbone timeout	2019-01-29 12:47:11 +01:00
Florent Kermarrec	05dcb5cadc	soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles	2019-01-27 08:28:01 +01:00
Florent Kermarrec	0c687bc29e	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
Florent Kermarrec	96527b5a3a	soc/interconnect/stream/gearbox: remove bit reversing by changing words order	2018-11-30 23:12:30 +01:00
enjoy-digital	4592e3235b	Merge pull request #128 from mithro/small-fix ... Two small fixes	2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell	4f565c5179	stream.Endpoint: Pass extra arguments to superclass.	2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell	3b9e4c4df6	wishbone.SRAM: Support non-32bit wishbone widths.	2018-11-25 12:56:37 -08:00
Florent Kermarrec	7623b5dd96	soc/interconnect/stream/gearbox: inverse bit order	2018-11-23 18:34:24 +01:00
Florent Kermarrec	a5ed42ec68	soc/interconnect/stream: add Gearbox	2018-11-17 17:29:45 +01:00