Florent Kermarrec
ffd2be2ba0
csr: add we signal to CSR, CSRStatus
...
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.
This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
2019-09-24 17:51:06 +02:00
Sean Cross
60d8572c3e
csr_eventmanager: add name and description args
...
Add `name` and `description` as optional arguments to the various
EventSource types. These default to `None`, so this should be a
backwards-compatible change.
Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-19 17:23:03 +08:00
Florent Kermarrec
99ed0877ac
csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)
2019-09-18 10:47:54 +02:00
Florent Kermarrec
cca0478a5e
soc/cores/spi: use new CSRField (no functional change)
2019-09-16 17:02:55 +02:00
Florent Kermarrec
9bda614a3e
csr: update copyrights
2019-09-16 08:49:00 +02:00
Florent Kermarrec
29134cc659
csr: more documentation
2019-09-16 08:45:29 +02:00
Florent Kermarrec
74e756aa30
csr/CSRStorage: remove storage_full (was only needed by alignment_bits)
2019-09-16 08:38:26 +02:00
Florent Kermarrec
5dc440e80d
csr: use IntEnum for CSRAccess
2019-09-16 08:36:25 +02:00
Florent Kermarrec
d2646f138e
csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful
2019-09-15 19:47:48 +02:00
Florent Kermarrec
8e14694eb5
csr/fields: document, add separators, 100 characters per line
2019-09-15 19:11:25 +02:00
Florent Kermarrec
4e84729cf9
csr/fields: add access parameter
2019-09-14 22:16:18 +02:00
Florent Kermarrec
23b01f8f02
csr/fields: add pulse mode support
2019-09-14 21:49:34 +02:00
Florent Kermarrec
8c080e5fb6
soc/interconnect/csr: add initial field support
2019-09-13 20:01:31 +02:00
Florent Kermarrec
19f58dd971
interconnect/wishbone: add FlipFlop to allow UpConverter to be used
...
Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
2019-09-09 11:47:36 +02:00
Florent Kermarrec
67a09aef05
soc/interconnect/stream: add Monitor module
...
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
2019-09-05 11:54:14 +02:00
chmousset
db4c609a33
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 11:30:39 +02:00
Florent Kermarrec
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
...
Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
Florent Kermarrec
f4770219fa
soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs
2019-07-08 10:20:51 +02:00
Florent Kermarrec
4ee9c53f18
csr: add assert to ensure CSR size < busword (thanks tweakoz)
2019-07-03 13:44:15 +02:00
Florent Kermarrec
daa4307d9e
add CONTRIBUTORS file and add copyright header to all files
2019-06-23 23:23:56 +02:00
Florent Kermarrec
08a811b1a5
soc/interconnect/gearbox: add msb_first/lsb_first order
2019-05-29 10:25:25 +02:00
Florent Kermarrec
5109511259
soc/interconnect/axi: add round/robin arbitration between writes/reads
2019-05-25 10:02:31 +02:00
Florent Kermarrec
67159349d6
soc/interconnect: remove axi_lite
...
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
Florent Kermarrec
0714816f31
soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone
2019-05-03 11:59:06 +02:00
Florent Kermarrec
c6d0d23445
soc/interconnect/axi: add AXI Lite definition
2019-05-03 09:43:12 +02:00
Florent Kermarrec
9fab4752c4
soc/interconnect/axi: add comment on axi signas that are present but not used
2019-05-03 09:30:59 +02:00
Florent Kermarrec
6cf1ff091c
soc/interconnect/axi: connect axi.ar/aw when selecting write or read
2019-05-02 09:58:55 +02:00
Florent Kermarrec
6affc56a09
soc/interconnect/axi: wishbone address shift is not always 2, make it generic
2019-05-02 09:35:07 +02:00
Florent Kermarrec
698bc88296
soc/interconnect/wishbone: allow setting adr_width (default to 30)
2019-05-02 09:34:30 +02:00
Florent Kermarrec
4dccb8a9eb
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
2019-05-01 12:59:04 +02:00
Florent Kermarrec
5c1d980540
soc/interconnect/axi: add burst support to AXI2Wishbone
2019-04-29 16:49:20 +02:00
Florent Kermarrec
6de2713524
soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
2019-04-29 14:02:05 +02:00
Florent Kermarrec
9cbed91b3e
soc/interconnect/axi: add AXIBurst2Beat
...
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
Florent Kermarrec
5a8115d9e1
soc/interconnect/avalon: add description
2019-04-19 11:43:15 +02:00
Florent Kermarrec
a92e90b215
soc/interconnect: add avalon with converters to/from native streams
2019-04-18 18:42:29 +02:00
Florent Kermarrec
b15fd9d834
interconnect/axi: add missing axi signals
2019-04-01 10:23:25 +02:00
Gabriel L. Somlo
449632e430
soc/interconnect/axi: data/address length cleanup
...
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
2019-03-27 16:52:52 -04:00
Florent Kermarrec
552b0243b3
soc/interconnect/axi: remove dead code (thanks gsomlo)
2019-03-27 21:15:14 +01:00
Florent Kermarrec
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
Florent Kermarrec
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
Florent Kermarrec
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
Florent Kermarrec
57b8bdd530
soc/integration/soc_core: allow disabling wishbone timeout
2019-01-29 12:47:11 +01:00
Florent Kermarrec
05dcb5cadc
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
2019-01-27 08:28:01 +01:00
Florent Kermarrec
0c687bc29e
soc/interconnect/stream: add support for buffered async fifo
2018-12-08 01:24:08 +01:00
Florent Kermarrec
96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
enjoy-digital
4592e3235b
Merge pull request #128 from mithro/small-fix
...
Two small fixes
2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
Florent Kermarrec
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
Florent Kermarrec
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
Florent Kermarrec
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
Florent Kermarrec
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
Florent Kermarrec
ef1c778446
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
2018-07-10 13:29:32 +02:00
Florent Kermarrec
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
Sergiusz Bazanski
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
Florent Kermarrec
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
Florent Kermarrec
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
Florent Kermarrec
db6c88bbef
soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases)
2017-10-12 11:30:56 +02:00
Florent Kermarrec
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
Florent Kermarrec
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
Florent Kermarrec
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
Florent Kermarrec
5efd6a8412
soc/interconnect/stream_packet.py: make error payload optional on Packetizer
2017-03-28 12:21:54 +02:00
Florent Kermarrec
ff31959aea
merge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-13 03:55:00 +01:00
Florent Kermarrec
30f7dd69bd
soc/interconnect/stream/: add busy signal to PipelinedActor
2017-01-10 02:18:21 +01:00
Florent Kermarrec
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
Florent Kermarrec
e6681bbb9c
soc/interconnect/wishbone: add FlipFlop (should be removed)
2016-04-25 19:14:20 +02:00
Florent Kermarrec
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
Florent Kermarrec
3d222d9e63
soc/interconnect/dma_lasmi: change endpoint names
2016-04-13 18:28:52 +02:00
Florent Kermarrec
b2eaf412c1
soc/interconnect/stream/PipelinedActor: add latency attribute
2016-04-07 12:10:32 +02:00
Florent Kermarrec
1d4f44e7db
soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores
2016-03-31 00:02:22 +02:00
Florent Kermarrec
9517b9b870
soc/interconnect/stream_sim: use passive generators and some cleanup
2016-03-23 01:04:33 +01:00
Florent Kermarrec
cf29ee0b91
soc/interconnect/stream_sim: adapt to new simulator
2016-03-21 19:56:43 +01:00
Florent Kermarrec
71a719be44
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 20:13:47 +01:00
Florent Kermarrec
9032665750
soc/interconnect/wishbonebridge: fix import
2016-03-16 19:34:50 +01:00
Florent Kermarrec
d7112efdba
soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now)
2016-03-16 19:33:29 +01:00
Florent Kermarrec
39aacf2df4
soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring
2016-03-16 19:33:00 +01:00
Florent Kermarrec
e0e2427795
soc: replace all Sink/Source with stream.Endpoint
2016-03-16 18:05:57 +01:00
Florent Kermarrec
c860581b86
soc/interconnect/stream: use new Converter/StrideConverter
2016-03-16 17:00:58 +01:00
Florent Kermarrec
8c272c1f6f
soc/interconnect/stream: fix missing param
2016-03-16 16:21:32 +01:00
Florent Kermarrec
cb47373383
soc/interconnect/stream: remove packetized parameter and use of sop
2016-03-16 11:54:28 +01:00
Florent Kermarrec
44a5b95281
soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter)
2016-03-15 15:52:57 +01:00
Florent Kermarrec
2218ece98a
soc/interconnect/stream: fix merge issue (missing params connect)
2016-02-01 00:08:27 +01:00
Florent Kermarrec
0498a31818
some cleanup
...
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
2015-12-27 13:09:58 +01:00
Florent Kermarrec
6ea65f957c
soc/interconnect/stream: expose Endpoint
2015-12-19 21:49:45 +01:00
Florent Kermarrec
f6aeb6e41a
soc/interconnect/stream: improve Pipeline to allow passing endpoints
2015-11-28 18:31:47 +01:00
Florent Kermarrec
d85d2b7b9b
soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
2015-11-27 20:14:01 +01:00
Florent Kermarrec
7298fff1e6
soc/interconnect/stream_packet: fix Counter removing
2015-11-24 20:30:53 +01:00
Florent Kermarrec
71483b8935
soc/tools: initialize wishbone remote control (for now only uart)
2015-11-17 01:05:52 +01:00
Florent Kermarrec
1f80bb9561
soc/interconnect/stream_packet: remove Counter
2015-11-16 16:53:23 +01:00
Florent Kermarrec
ec35290c45
soc/interconnect/wishbonebridge: remove Counter
2015-11-16 16:48:37 +01:00
Florent Kermarrec
2f52d364af
soc/interconnect/stream/SyncFIFO: expose fifo level
2015-11-16 16:11:31 +01:00
Florent Kermarrec
3a2e6117f4
soc/interconnect/stream: add Cast and others small fixes
2015-11-14 12:17:09 +01:00
Florent Kermarrec
16ba646b1b
add TODOs
2015-11-14 03:15:10 +01:00
Florent Kermarrec
032f5a9620
soc/interconnect: add stream_sim
2015-11-14 00:43:49 +01:00
Florent Kermarrec
ba959c832d
soc/interconnect: rename packet to stream_packet
2015-11-14 00:42:58 +01:00
Florent Kermarrec
fc3ffe87ac
for now use our fork of migen (to be able to simulate our designs)
2015-11-13 18:31:46 +01:00
Florent Kermarrec
7d6cee6751
soc/interconnect/stream: add BufferizeEndpoints
2015-11-12 18:54:15 +01:00
Florent Kermarrec
83427c87cd
soc/interconnect/stream: add Pipeline
2015-11-12 01:41:23 +01:00
Florent Kermarrec
81c6facca2
soc/interconnect/stream: reintroduce params
2015-11-12 01:12:15 +01:00
Florent Kermarrec
f6b30fcae2
soc/interconnect: add packet
2015-11-12 00:54:40 +01:00
Florent Kermarrec
525da89c7d
soc/interconnect: add wishbonebridge and uart bridge
2015-11-12 00:52:36 +01:00
Florent Kermarrec
89b189ce4a
soc/interconnect/stream: reintroduce PipelinedActor/Buffer
2015-11-12 00:51:32 +01:00
Florent Kermarrec
619cd8e695
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
2015-11-11 12:10:55 +01:00
Florent Kermarrec
3f43a49382
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
...
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
2015-11-10 16:51:51 +01:00
Florent Kermarrec
6a0f85dc42
litex: reorganize things, first work working version
2015-11-07 17:48:55 +01:00
