Sebastien Bourdeauducq
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cbc387f69e
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actorlib/sim/SimActor: remove dead time between transactions
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2012-06-20 22:39:52 +02:00 |
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Sebastien Bourdeauducq
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6aff41a883
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actorlib/structuring/Pack: drive busy signal
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2012-06-20 22:39:03 +02:00 |
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Sebastien Bourdeauducq
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34d8ae3c11
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flow: perftools
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2012-06-20 21:59:17 +02:00 |
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Sebastien Bourdeauducq
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6fac3f027f
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examples/dataflow: structuring test
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2012-06-20 18:25:01 +02:00 |
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Sebastien Bourdeauducq
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7d0e179a03
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actorlib: structuring (untested)
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2012-06-20 16:35:01 +02:00 |
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Sebastien Bourdeauducq
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1576cb0950
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actorlib/control: simplify + fix
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2012-06-17 21:19:47 +02:00 |
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Sebastien Bourdeauducq
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66ac62d0bb
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flow/network: fix handling of edges with subrecords at both ends
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2012-06-17 18:31:45 +02:00 |
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Sebastien Bourdeauducq
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75d569a12c
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actorlib/control: use numbers of bits instead of maxima
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2012-06-17 18:29:57 +02:00 |
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Sebastien Bourdeauducq
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4873cfe1a7
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flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor
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2012-06-17 13:45:18 +02:00 |
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Sebastien Bourdeauducq
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98c9da95d1
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flow/network: handle default endpoints correctly in _infer_plumbing_layout
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2012-06-16 22:41:15 +02:00 |
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Sebastien Bourdeauducq
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9af87367eb
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flow/network: require ActorNode be passed to add_connection
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2012-06-16 22:40:26 +02:00 |
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Sebastien Bourdeauducq
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b0b0380ea7
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flow/network: fix ActorNode default params
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2012-06-16 22:39:31 +02:00 |
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Sebastien Bourdeauducq
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1a576e5c83
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flow/actor: fix busy signal generation for pipelined actors
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2012-06-16 22:38:45 +02:00 |
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Sebastien Bourdeauducq
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9228e8a96d
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flow/actor: add single_sink/single_source retrieval methods
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2012-06-16 22:38:16 +02:00 |
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Sebastien Bourdeauducq
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c1450daa93
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flow: insert splitters
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2012-06-16 21:23:42 +02:00 |
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Sebastien Bourdeauducq
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bde8361e19
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flow: insert combinators and infer plumbing layout
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2012-06-16 17:30:54 +02:00 |
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Sebastien Bourdeauducq
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da522cd58d
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Abstract actor graphs
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2012-06-15 17:52:19 +02:00 |
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Sebastien Bourdeauducq
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b14be4c8a3
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actorlib: ASMI sequential reader
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2012-06-12 21:04:47 +02:00 |
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Sebastien Bourdeauducq
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ce9e35b8ef
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fix SimActor get_fragment
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2012-06-12 17:52:08 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
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PureSimulable
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2012-06-12 17:08:56 +02:00 |
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Sebastien Bourdeauducq
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a591510189
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ASMI simulation models
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2012-06-12 16:57:00 +02:00 |
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Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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f061b25a24
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bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
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Sebastien Bourdeauducq
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009f26bb9d
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flow/network: refactor graph
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2012-06-08 22:49:49 +02:00 |
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Sebastien Bourdeauducq
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de408b2cba
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flow/ala: fix typo
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2012-06-08 22:48:47 +02:00 |
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Sebastien Bourdeauducq
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356051e8a8
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actorlib: WB reader simulation OK
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2012-06-08 21:31:05 +02:00 |
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Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
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Sebastien Bourdeauducq
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152a7e282e
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actorlib/sim: use set instead of list to represent active transactions
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2012-06-08 17:56:52 +02:00 |
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Sebastien Bourdeauducq
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910c7806cf
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actorlib: generator-based generic simulation actor
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2012-06-08 17:54:03 +02:00 |
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Sebastien Bourdeauducq
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b145f9e5e2
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sim: multiread/multiwrite
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2012-06-08 17:52:32 +02:00 |
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Sebastien Bourdeauducq
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f38ef626de
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corelogic/record: better repr
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2012-06-08 17:49:31 +02:00 |
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Sebastien Bourdeauducq
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1c0f636c8d
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flow: generic parameter passing to Actor from sequential/pipelined
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2012-06-07 18:24:33 +02:00 |
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Sebastien Bourdeauducq
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a1fc86af8f
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flow: fix actor repr
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2012-06-07 15:48:35 +02:00 |
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Sebastien Bourdeauducq
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680a34465d
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flow: refactor scheduling models
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2012-06-07 14:44:43 +02:00 |
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Sebastien Bourdeauducq
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493b181af1
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bank/description: pad unaligned multi-word registers at the top
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2012-05-21 22:55:23 +02:00 |
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Sebastien Bourdeauducq
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9449bbea0a
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Add LICENSE file
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2012-05-21 19:56:23 +02:00 |
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Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
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Sebastien Bourdeauducq
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0bea1e2589
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asmi: dat_wm high to disable data write
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2012-05-15 14:41:54 +02:00 |
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Sebastien Bourdeauducq
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f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
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398ece8fe2
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fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
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2012-04-30 16:38:40 -05:00 |
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Sebastien Bourdeauducq
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0b62e573ae
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sim: pass extra keyword arguments to Verilog converter
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2012-04-30 16:38:17 -05:00 |
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Sebastien Bourdeauducq
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6a52e44d09
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fhdl: support len() on signals
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2012-04-08 18:06:22 +02:00 |
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Sebastien Bourdeauducq
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b9c533be51
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bank/csrgen: allow specifying existing CSR interface
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2012-04-06 14:59:09 +02:00 |
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Sebastien Bourdeauducq
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2a4e49e381
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fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
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Sebastien Bourdeauducq
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623e8e436a
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fhdl/verilog: do not attempt to initialize instance and mem output signals
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2012-04-02 12:59:42 +02:00 |
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Sebastien Bourdeauducq
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6e3b25ebb6
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
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Sebastien Bourdeauducq
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d3c6b8d16f
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sim/proxy: support lists
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2012-04-01 17:19:53 +02:00 |
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Sebastien Bourdeauducq
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f3ae22f488
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fhdl/verilog: initialize internal read-only signals with their reset values
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2012-04-01 16:39:11 +02:00 |
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Sebastien Bourdeauducq
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0dfc215fe8
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corelogic/roundrobin: handle correctly special case with 1 request source
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2012-03-31 18:01:40 +02:00 |