Sebastien Bourdeauducq
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692794a21f
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flow: use Module and new Record APIs
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2013-04-10 19:12:42 +02:00 |
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Sebastien Bourdeauducq
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843f8a5bfc
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platforms: add Papilio Pro
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2013-04-08 20:28:23 +02:00 |
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Sebastien Bourdeauducq
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715d332c3d
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crg: apply constraint to IO pins, not internal signals
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2013-04-08 20:28:11 +02:00 |
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Sebastien Bourdeauducq
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20bdd424c8
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flow: adapt to new Record API
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2013-04-01 22:15:23 +02:00 |
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Sebastien Bourdeauducq
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29b468529f
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bus: replace simple bus module with new bidirectional Record
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2013-04-01 21:54:21 +02:00 |
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Sebastien Bourdeauducq
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6a3c413717
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New bidirectional-capable Record API
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2013-04-01 21:53:33 +02:00 |
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Sebastien Bourdeauducq
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c4f4143591
|
New CSR API
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2013-03-30 17:28:41 +01:00 |
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Sebastien Bourdeauducq
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633e5e6747
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fhdl/module/finalize: pass additional args to do_finalize
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2013-03-30 11:29:46 +01:00 |
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Sebastien Bourdeauducq
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8cf7c96a53
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crg: use new platform.request
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2013-03-26 23:08:35 +01:00 |
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Sebastien Bourdeauducq
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38e92eb92b
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altera_quartus: fix clock domain name
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2013-03-26 23:05:46 +01:00 |
|
Sebastien Bourdeauducq
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3b19dfc412
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Support for platform info
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2013-03-26 19:17:35 +01:00 |
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Sebastien Bourdeauducq
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74cc4d22cd
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generic_platform: remove obj in request + add lookup_request
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2013-03-26 17:56:53 +01:00 |
|
Sebastien Bourdeauducq
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574becc1fc
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fhdl/specials: clean up clock domain handling
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2013-03-26 11:58:34 +01:00 |
|
Sebastien Bourdeauducq
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77a0f0a3bb
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actorlib/structuring/Cast: support inversion
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2013-03-25 15:54:09 +01:00 |
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Sebastien Bourdeauducq
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c4c4765a4e
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bank/csrgen/BankArray: retain name information
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2013-03-25 14:44:15 +01:00 |
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Sebastien Bourdeauducq
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53edc3557e
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bank/description/Register: add get_size
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2013-03-25 14:43:44 +01:00 |
|
Sebastien Bourdeauducq
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3da98ea04d
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genlib/record: use getattr instead of __dict__
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2013-03-24 00:51:01 +01:00 |
|
Sebastien Bourdeauducq
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1897b74f97
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genlib/record: add eq
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2013-03-24 00:50:33 +01:00 |
|
Sebastien Bourdeauducq
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003f1950cd
|
xilinx_ise: fix clock domain names
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2013-03-23 19:37:16 +01:00 |
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Sebastien Bourdeauducq
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9d7c679b8c
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genlib/fifo: simple synchronous FIFO
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2013-03-22 18:18:38 +01:00 |
|
Sebastien Bourdeauducq
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ca431fc7c2
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fhdl/module: support clock domain remapping of submodules
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2013-03-22 18:17:54 +01:00 |
|
Sebastien Bourdeauducq
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a94bf3b2c5
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genlib/cdc/MultiReg: output clock domain defaults to sys
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2013-03-21 10:40:02 +01:00 |
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Sebastien Bourdeauducq
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b38818eb17
|
examples/sim/fir: convert to new API
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2013-03-19 11:46:27 +01:00 |
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Sebastien Bourdeauducq
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17f2b17654
|
fhdl/verilog: optionally disable clock domain creation
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2013-03-18 18:45:19 +01:00 |
|
Sebastien Bourdeauducq
|
797411c1a9
|
generic_platform: do not create clock domains during Verilog conversion
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2013-03-18 18:44:58 +01:00 |
|
Sebastien Bourdeauducq
|
af4eb02551
|
examples/basic/arrays: demonstrate lowering of Array in Instance expression
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2013-03-18 18:37:23 +01:00 |
|
Sebastien Bourdeauducq
|
7a06e9457c
|
Lowering of Special expressions + support ClockSignal/ResetSignal
|
2013-03-18 18:36:50 +01:00 |
|
Sebastien Bourdeauducq
|
dc55289323
|
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
|
2013-03-18 14:38:01 +01:00 |
|
Sebastien Bourdeauducq
|
e95d2f4779
|
fhdl/tools/value_bits_sign: support not
|
2013-03-18 09:52:43 +01:00 |
|
Sebastien Bourdeauducq
|
b6fe3ace05
|
fhdl/structure: style fix
|
2013-03-17 15:33:38 +01:00 |
|
Sébastien Bourdeauducq
|
2a4cc3875c
|
Merge pull request #6 from larsclausen/master
Minor improvements
|
2013-03-17 07:33:14 -07:00 |
|
Sebastien Bourdeauducq
|
4bf3190244
|
MultiReg: remove idomain
|
2013-03-15 19:54:25 +01:00 |
|
Sebastien Bourdeauducq
|
2f522bdd9f
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genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
|
2013-03-15 19:50:24 +01:00 |
|
Sebastien Bourdeauducq
|
e2d156ef64
|
genlib/cdc/MultiReg: remove idomain
|
2013-03-15 19:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
7b49fd9386
|
fhdl/specials: fix rename_clock_domain declarations
|
2013-03-15 19:47:01 +01:00 |
|
Sebastien Bourdeauducq
|
51bec340ab
|
sim: remove PureSimulable (superseded by Module)
|
2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
dd0f3311cd
|
structure: remove Fragment.call_sim
|
2013-03-15 19:15:48 +01:00 |
|
Sebastien Bourdeauducq
|
9b9bd77d00
|
sim: compatibility with new ClockDomain API
|
2013-03-15 19:15:28 +01:00 |
|
Sebastien Bourdeauducq
|
6feb6e60b0
|
New clock_domain API
|
2013-03-15 18:46:11 +01:00 |
|
Sebastien Bourdeauducq
|
208e039bbb
|
Local clock domain example
|
2013-03-15 18:18:32 +01:00 |
|
Sebastien Bourdeauducq
|
bd8bbd9305
|
Make ClockDomains part of fragments
|
2013-03-15 18:17:33 +01:00 |
|
Sebastien Bourdeauducq
|
001beadb97
|
altera_quartus, de0nano: add copyright notices
|
2013-03-15 12:37:25 +01:00 |
|
Sebastien Bourdeauducq
|
f9e07b92a4
|
Added platform file for DE0 Nano (by Florent Kermarrec)
|
2013-03-15 11:41:38 +01:00 |
|
Sebastien Bourdeauducq
|
86d6f1d011
|
Added support for Altera Quartus (by Florent Kermarrec)
|
2013-03-15 11:32:12 +01:00 |
|
Sebastien Bourdeauducq
|
71c8172836
|
xilinx_ise/CRG_SE: reset inversion support
|
2013-03-15 11:31:36 +01:00 |
|
Sebastien Bourdeauducq
|
37d8029848
|
CRG: support reset inversion
|
2013-03-15 10:49:18 +01:00 |
|
Sebastien Bourdeauducq
|
24910173b7
|
CRG: use new Module API
|
2013-03-15 10:48:43 +01:00 |
|
Sebastien Bourdeauducq
|
5adab17efa
|
flow/actor/filter_endpoints: deterministic order
|
2013-03-14 12:20:18 +01:00 |
|
Sebastien Bourdeauducq
|
fc883198ae
|
bank/csrgen/BankArray: create banks in sorted order
|
2013-03-13 23:07:44 +01:00 |
|
Sebastien Bourdeauducq
|
52d13959f2
|
bank/description: modify reg/mem in-place
|
2013-03-13 19:46:34 +01:00 |