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3405 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 75ef2f9004 fix most imports 2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq f69674e89c interconnect: add bus/bank components from Migen 2015-09-24 20:48:18 +08:00
Sebastien Bourdeauducq af88a7a3f9 setup: simpler version check, beta status 2015-09-24 16:08:39 +08:00
Sebastien Bourdeauducq ecdc4101b4 lasmicon: enable refresh at all times 2015-09-24 16:01:08 +08:00
Sebastien Bourdeauducq 9b08b037e4 break down sdram, improve consistency of core names 2015-09-24 15:59:55 +08:00
Sebastien Bourdeauducq 0f410e45f1 cores directory 2015-09-24 09:05:10 +08:00
Sebastien Bourdeauducq 83509163df reorganization WIP: flatten core structure (SDRAM still needs to be done) 2015-09-24 00:18:27 +08:00
Sebastien Bourdeauducq 33f344b92a fsm: NextState and NextValue should derive from _Statement 2015-09-23 22:38:10 +08:00
Sebastien Bourdeauducq 8935ca2c9f setup: remove unneeded import 2015-09-23 09:52:24 +08:00
Sebastien Bourdeauducq 01be953e30 setup: cleanup 2015-09-23 09:52:12 +08:00
Sebastien Bourdeauducq 030998658d setup: convert to unix eols 2015-09-23 09:50:31 +08:00
Sebastien Bourdeauducq 74b3e16dd0 CONTRIBUTING.md->rst 2015-09-23 00:57:36 +08:00
Sebastien Bourdeauducq 8421549935 README.md->rst 2015-09-23 00:55:37 +08:00
Sebastien Bourdeauducq 82236d9b40 migen.fhdl.std -> migen 2015-09-23 00:36:47 +08:00
Sebastien Bourdeauducq bd74d39338 misoclib -> misoc 2015-09-23 00:35:02 +08:00
Sebastien Bourdeauducq 8534562185 sim: fix slice assign 2015-09-22 20:33:44 +08:00
Sebastien Bourdeauducq 88f9d72e74 conda: use new branch (revert this after merge) 2015-09-22 17:27:44 +08:00
Sebastien Bourdeauducq 6005548df6 setup.py: cleanup 2015-09-22 17:27:27 +08:00
Sebastien Bourdeauducq 31ffa8c18f fsm: support complex targets in NextValue. Closes #27. 2015-09-22 16:55:24 +08:00
Sebastien Bourdeauducq 1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24 2015-09-22 14:30:16 +08:00
Rohit Kumar Singh 71993edae4 Add init file in sdram/phy dir 
Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory

More info here: https://bitbucket.org/pypa/setuptools/issues/97
 2015-09-21 23:46:16 +08:00
Sebastien Bourdeauducq 2c1553fea2 sim: insert resets, support ClockSignal and ResetSignal 2015-09-21 22:13:36 +08:00
Sebastien Bourdeauducq 99af825a5a sim: drive clock signals 2015-09-21 21:53:41 +08:00
Sebastien Bourdeauducq a67b4baa0c sim: VCD output support 2015-09-21 21:20:31 +08:00
Sebastien Bourdeauducq 34ce6b077f verilog: remove unneeded import 2015-09-21 21:19:58 +08:00
Sebastien Bourdeauducq b8647a161d doc: minor edits 2015-09-21 21:19:39 +08:00
Florent Kermarrec b2a4eead0c uart/software: remove litescope dependency 2015-09-21 09:04:59 +02:00
Tim 'mithro' Ansell bc1450e4f2 Adding --help option to flterm. 2015-09-21 11:02:36 +08:00
Sebastien Bourdeauducq 2ac748aef2 doc: remove spurious file 2015-09-20 16:13:08 +08:00
Sebastien Bourdeauducq 74b0cfc83b doc: remove outdated or moved parts, cleanup 2015-09-20 16:10:40 +08:00
Sebastien Bourdeauducq 1767eef9cb fhdl/visit: support Constant 2015-09-20 16:10:17 +08:00
Sebastien Bourdeauducq 87a8531952 travis: VPI is not there for now 2015-09-20 15:12:04 +08:00
Sebastien Bourdeauducq 7f767095ec sim: support generators yielding statements 2015-09-20 15:04:15 +08:00
Sebastien Bourdeauducq 320dffb4ac sim: memory access from generators 2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq 59802bec76 fhdl/structure: add missing init 2015-09-20 14:46:30 +08:00
Sebastien Bourdeauducq 8bbfaa01fc sim: memory support 2015-09-19 23:21:46 +08:00
Sebastien Bourdeauducq 1861ae9d01 fhdl/specials: MemoryPort.clock should always be a ClockSignal 2015-09-19 23:21:24 +08:00
Sebastien Bourdeauducq 262fd50677 fhdl/simplify: add MemoryToArray 2015-09-19 23:20:57 +08:00
Sebastien Bourdeauducq 944a0b0480 test/fifo: convert to new API 2015-09-19 23:20:30 +08:00
Sebastien Bourdeauducq dcf4f7fef3 genlib/fifo: add missing import 2015-09-19 23:20:19 +08:00
Sebastien Bourdeauducq 9420aabc0d sim: support arrays, and cat+slice in assignment target 2015-09-19 14:56:26 +08:00
Sebastien Bourdeauducq ef92aa35f2 Merge branch 'master' of github.com:m-labs/migen 2015-09-19 12:22:47 +08:00
Florent Kermarrec 563231fdfb migen/genlib/cdc: fix BusSynchronizer 
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
 2015-09-19 12:21:54 +08:00
Florent Kermarrec 210ba91d58 migen/genlib/cdc: fix BusSynchronizer 
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
 2015-09-19 12:18:39 +08:00
Sebastien Bourdeauducq bfcc8f9661 sim: remove unneeded import 2015-09-19 12:18:20 +08:00
Sebastien Bourdeauducq 84f98b4632 genlib/CRG: fix variable name conflict 2015-09-19 11:18:44 +08:00
Sebastien Bourdeauducq 0a55ef5bc3 test: add divider 2015-09-18 11:07:14 +08:00
Florent Kermarrec e4329c739c actorlib/structuring: fix Pack in packetized mode 
Params need to be registered for the case when eop appears before the end of the pack cycle.
 2015-09-18 02:28:02 +02:00
Sebastien Bourdeauducq ec1d4edf84 sim: support Case 2015-09-17 17:25:06 +08:00
Sebastien Bourdeauducq 9d3fd50950 sim: variables are deprecated 2015-09-17 17:24:57 +08:00