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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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643f3f9a93 test_i2c: add more commands Radek Pesina 2023-08-30 09:58:06 +1000
f99658200e soc/cores/i2c: rewrite state machine Andrew Dennison 2023-08-29 17:31:28 +1000
13811aeacb test_i2c: update to use improved _MockTristate Andrew Dennison 2023-08-28 15:49:49 +1000
b779933a5f test_i2c: improve and document _MockTristate* Andrew Dennison 2023-08-28 15:40:19 +1000
dce152b348 soc/cores/i2c: change SDA 1 or 2 cycles earlier Andrew Dennison 2023-08-28 14:26:59 +1000
e36946b251 soc/cores/i2c: convert to LiteXModule and name some components Andrew Dennison 2023-08-28 12:57:19 +1000
c867d5647b soc/cores/i2c: only change SDA when SCL is stable Andrew Dennison 2023-08-25 15:24:03 +1000
aef6cb3103 soc/cores/i2c: remove unnecessary code Andrew Dennison 2023-08-24 08:49:21 +1000
64ccd6df1c test_i2c: allow unit test to run directly Andrew Dennison 2023-08-25 15:25:37 +1000
5504cc626f soc/cores/i2c: change ISR to rising edge of idle Richard Tucker 2023-02-10 12:50:25 +1100
b8b6ecef7c soc/cores/i2c: fix CSR generation Richard Tucker 2023-02-10 12:49:57 +1100
90128756f9 test_i2c: test reading config Andrew Dennison 2023-02-01 10:53:09 +1100
ad37e17743 soc/cores/i2c: add interrupt Andrew Dennison 2023-01-17 10:58:41 +1100
4ddab34714 test_i2c: generate i2c.vcd Andrew Dennison 2023-01-13 15:48:06 +1100
a079da922a soc/cores: adapt misoc i2c to litex Andrew Dennison 2023-01-13 12:57:27 +1100
9dc3eefb7d soc/cores/i2c: import from misoc Andrew Dennison 2023-01-13 13:37:48 +1100
a014c4f07c tools/litex_sim: Cleanup imports. Florent Kermarrec 2024-07-18 12:16:23 +0200
8a08d5ca19

Merge pull request #2017 from Dolu1990/vexiiriscv Dolu1990 2024-07-18 11:37:03 +0200
cbe7413fee Fix VexiiRiscv Dolu1990 2024-07-18 11:32:07 +0200
1b9bdbdce4

Merge pull request #2016 from Dolu1990/vexiiriscv enjoy-digital 2024-07-18 11:27:20 +0200
f687425cb1 Update VexiiRiscv Dolu1990 2024-07-18 11:26:13 +0200
473784581d

Merge pull request #2011 from Dolu1990/vexiiriscv Dolu1990 2024-07-12 17:29:45 +0200
9fa1b4c123 Update Nax/Vexii Dolu1990 2024-07-12 16:17:30 +0200
aef5a2094e soc/cores/video: Add additional color formats inc 2024-07-10 15:21:51 +0200
22ff3ac42d Merge branch 'master' into vexiiriscv Dolu1990 2024-07-10 09:37:43 +0200
1267ba8ae6 Update Nax/Vexii Dolu1990 2024-07-10 09:35:34 +0200
e4e9bd2125 interconnect/axi/axi_lite: Add bursting property even if always False. Florent Kermarrec 2024-07-09 17:02:54 +0200
372ab25273 Merge branch 'nax64_irq' into vexiiriscv Dolu1990 2024-07-09 15:18:25 +0200
549d23e4f7 build/efinix: Add default parameter values and fix other typos. Florent Kermarrec 2024-07-09 10:04:03 +0200
e6171e79db build/efinix: Fix typos (thanks @AndrewD). Florent Kermarrec 2024-07-09 10:00:21 +0200
7de4f01aa8

Merge pull request #2009 from trabucayre/efinix_args_opts enjoy-digital 2024-07-08 17:01:28 +0200
ec1528fb69 build/efinix: added argument to change synthesis options configurations Gwenhael Goavec-Merou 2024-07-08 15:59:30 +0200
0db650ac6a soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic). Florent Kermarrec 2024-07-05 13:55:58 +0200
3c2ddd1655 cores/can/ctu_can_fd: Remove pads.irq that was used as debug. Florent Kermarrec 2024-07-05 09:34:36 +0200
7ec35eb4c5

Merge pull request #2007 from enjoy-digital/ctu-can-fd enjoy-digital 2024-07-05 09:16:21 +0200
d838a9ca73

Merge pull request #2006 from trabucayre/update_altera_build enjoy-digital 2024-07-04 13:04:15 +0200
9fd63973aa build/altera/quartus.py: added support for ips other than QSYS_FILE Gwenhael Goavec-Merou 2024-07-04 09:51:09 +0200
7393c35264 build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn Gwenhael Goavec-Merou 2024-07-04 09:50:06 +0200
b286fe5621

Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs enjoy-digital 2024-07-04 09:10:27 +0200
d4d1a1bfd7 gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog. Florent Kermarrec 2024-07-03 21:44:31 +0200
aac828b4cb soc/add_etherbone: Update ethmac. Florent Kermarrec 2024-07-02 17:10:32 +0200
b285992fb1 litex_json2dts_zephyr.py: Remove unnessesary configs Fin Maaß 2024-07-02 15:04:50 +0200
2a83bce63e cores/dma: Automatically call add_ctrl method in add_csr is ctrl are not present. Florent Kermarrec 2024-07-01 18:22:41 +0200
9c07b45f3c soc/add_ethernet: Add 64-bit data_width support. Florent Kermarrec 2024-06-27 09:35:28 +0200
3dd3477ea2

Merge pull request #2004 from enjoy-digital/wishbone_dma_ctrl enjoy-digital 2024-06-26 18:46:01 +0200
4b745f9eba soc/cores/dma: Add default parameters to add_ctrl. wishbone_dma_ctrl Florent Kermarrec 2024-06-26 17:57:47 +0200
01a15e4bbf soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. Florent Kermarrec 2024-06-26 16:13:45 +0200
23a0d8fa2a soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. Florent Kermarrec 2024-06-26 16:06:42 +0200
06a26b7c9b

Merge pull request #2003 from enjoy-digital/liteeth_wishbone_tx_rx_buses enjoy-digital 2024-06-25 19:05:49 +0200
14a640302c integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. liteeth_wishbone_tx_rx_buses Florent Kermarrec 2024-06-25 17:39:26 +0200
1ad0f828bb soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design. Florent Kermarrec 2024-06-25 15:07:05 +0200
462016a1d0 litex/tools/litex_json2dts_linux: Add initial CAN support. ctu-can-fd Florent Kermarrec 2024-06-24 13:01:18 +0200
71ff4eaadc soc/cores/can: Switch to our fork of CTU-CAN-FD, remove debug signals and do a git clone if not present in execution directory. Florent Kermarrec 2024-06-24 12:53:38 +0200
bad64bcf6d soc/cores: Add initial CTU-CAN-FD integration from 2021 work with recent updates/tests. Florent Kermarrec 2024-06-24 12:27:17 +0200
8afa36f24a CHANGES.md: Update and add Issue/PR number. Florent Kermarrec 2024-06-24 10:52:34 +0200
a47dde6fbc

Merge pull request #1999 from FlyGoat/csr-re enjoy-digital 2024-06-24 10:36:48 +0200
8e4f8781f7

Merge pull request #1996 from VOGL-electronic/litex_watchdog enjoy-digital 2024-06-24 10:32:48 +0200
11537ec8cc

Merge pull request #2001 from rtucker85/master enjoy-digital 2024-06-24 09:05:34 +0200
21674ee29c

Merge pull request #1998 from FlyGoat/ahb-fixes enjoy-digital 2024-06-24 09:04:33 +0200
fd5a01dd26 integration/soc: Cleanup #1997. Florent Kermarrec 2024-06-24 09:03:24 +0200
5aad0d6aca

Merge pull request #1997 from FlyGoat/axi-id-fixes enjoy-digital 2024-06-24 09:00:31 +0200
a0763bf652 liblitespi: fix xor-used-as-pow bug Richard Tucker 2024-06-24 16:37:36 +1000
af3d2a29fc

csr_bus: Honour re signal from the upstream bus Jiaxun Yang 2024-06-23 15:58:39 +0100
9bdc22adfb

soc/integration/soc.py: Fix creation of AHB2Wishbone bridge Jiaxun Yang 2024-06-17 13:34:20 +0100
af19e210aa

soc/cores/cpu: Add Loongson GS232 MIPS CPU Jiaxun Yang 2024-06-17 19:59:22 +0100
b7ed16b190

sor/cores/cpu: Add CDIM MIPS CPU Jiaxun Yang 2024-06-17 14:56:05 +0100
bffbb4ffea

litex_setup: Implement mips_gcc_install Jiaxun Yang 2024-06-17 14:00:14 +0100
e90b7e8afd

soc/cores/cpu: Define MIPS triples Jiaxun Yang 2024-06-17 13:58:16 +0100
535f3cd7f1

bios: Use virtual address to access memory registers Jiaxun Yang 2024-06-17 13:32:20 +0100
4a01086e15

soc: Implement bios_map hook for CPU Jiaxun Yang 2024-06-17 13:31:04 +0100
22f9c063db

Merge pull request #1949 from alexey-morozov/master enjoy-digital 2024-06-23 09:03:17 +0200
3d530e0b59

integration/soc: data_width_convert: Inherit more bus properties Jiaxun Yang 2024-06-22 17:54:41 +0100
dd01a87653

Merge pull request #1993 from FlyGoat/jtag-patch enjoy-digital 2024-06-22 14:34:50 +0200
0559f3f033 core: add watchdog feature Fin Maaß 2024-06-20 16:38:38 +0200
29bdf6805f

Merge pull request #1840 from motec-research/parser_set_defaults_improvements enjoy-digital 2024-06-21 10:52:09 +0200
f40f63ae29

Merge pull request #1995 from VOGL-electronic/soc_spi_master_int enjoy-digital 2024-06-19 19:34:31 +0200
447469b0aa soc: add_spi_master: make spi_clk_freq an int Fin Maaß 2024-06-19 16:29:35 +0200
d9854582c6 build/lattice/radiant: allows extra configuration (prj_set_strategy_value XX=YY) to be added at script creation time Gwenhael Goavec-Merou 2024-06-19 16:22:30 +0200
d6b0c84f9c

Merge pull request #1992 from motec-research/fix_MockCSRRegion_base enjoy-digital 2024-06-19 09:13:49 +0200
e6353c8898

Merge pull request #1991 from motec-research/add_json_excludes enjoy-digital 2024-06-19 09:12:22 +0200
5a0fd6fb60 CHANGES.md: Update. Florent Kermarrec 2024-06-19 09:06:28 +0200
6fdf5a27d8

Merge pull request #1994 from trabucayre/zynqmp_peripheral_bus enjoy-digital 2024-06-19 08:48:03 +0200
146617eae8 soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default Gwenhael Goavec-Merou 2024-06-18 22:13:12 +0200
cc21c662ca soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default Gwenhael Goavec-Merou 2024-06-18 19:46:56 +0200
50c8ef07b6

jtagremote: Implement ntrst pin Jiaxun Yang 2024-06-18 14:18:28 +0100
f46ef03f42 build/openfpgaloader: print command before executing it to ease debugging/manual tests. Florent Kermarrec 2024-06-18 15:35:27 +0200
a8b3f36592

soc/cores/cpu: Implement add_jtag method Jiaxun Yang 2024-06-18 14:14:52 +0100
63d72a87e6 soc/cores/cpu/zynqmp/core.py: added CAN over EMIO support Gwenhael Goavec-Merou 2024-06-18 12:26:36 +0200
0d1d378966 soc/cores/cpu/zynqmp/core.py: added interrupts support Gwenhael Goavec-Merou 2024-06-18 10:59:42 +0200
0f7ea96812 build/parser: detect invalid defaults Andrew Dennison 2023-10-06 14:34:53 +1100
4730ee2288 build/parser: support set_default(cpu_type="xxx") Andrew Dennison 2023-09-11 12:30:58 +1000
dad04eedef integration/export: Fix MockCSRRegion base definition. Andrew Dennison 2024-04-02 10:42:44 +1100
56c284e9bc soc/integraion/builder: exclude some constants in add_json() Andrew Dennison 2024-06-04 10:41:53 +1000
702761d789 soc/integraion/builder: fix variable names Andrew Dennison 2024-06-04 10:38:38 +1000
485341a1cf soc/cores/cpu/zynq7000/core.py: fix missing CAN IO mode (security/nitpick) Gwenhael Goavec-Merou 2024-06-17 18:26:28 +0200
fba7ce42ec soc/cores/cpu/zynq7000/core.py: PS CANx support with EMIO pads Gwenhael Goavec-Merou 2024-06-17 18:09:00 +0200
6c4a756655 soc/cores/cpu/zynq7000/core.py: added GPx tcl configuration Gwenhael Goavec-Merou 2024-06-17 17:18:24 +0200
1335d3cebc soc/cores/cpu/zynq7000/core.py: enable F2P interrupts Gwenhael Goavec-Merou 2024-06-17 16:35:26 +0200
45928a3ce1 soc/cores/cpu/zynq7000/core.py: delayed filling ps7_tcl with config at finalize time Gwenhael Goavec-Merou 2024-06-17 16:29:23 +0200
3f095a260d Fix HP slave clock source and specify AXI version JoyBed 2024-06-16 18:50:55 +0200