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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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74b300597b cpu/naxriscv: fix 64 bits IRQ support Dolu1990 2024-05-16 18:59:40 +0200
60b0273eda Add baremetal IRQ support Dolu1990 2024-05-16 18:58:16 +0200
57f74da8d8 Merge branch 'master' into vexiiriscv Dolu1990 2024-05-16 16:17:21 +0200
d7b4c7bc9c

Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs enjoy-digital 2024-05-16 10:55:12 +0200
fbf03ec74c inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it. Florent Kermarrec 2024-05-16 10:36:07 +0200
c0d9224f09 integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled. Florent Kermarrec 2024-05-16 09:19:18 +0200
d4c1a10817 cores/cpu/naxriscv: Add baremetal IRQ support vexriscv_smp_irqs Dolu1990 2024-05-14 14:57:29 +0200
e03b097e8e software/libbase/isr.c: Simplify using __riscv_plic__ define. Florent Kermarrec 2024-05-14 14:47:01 +0200
c79e1ef95f cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag. Florent Kermarrec 2024-05-14 14:43:57 +0200
786c929f08 cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE Dolu1990 2024-05-14 14:24:37 +0200
8a83585b85

Merge pull request #1953 from enjoy-digital/export_csr_c_rework enjoy-digital 2024-05-14 12:54:48 +0200
8eaa53ae9a test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated). Florent Kermarrec 2024-05-14 12:53:09 +0200
c810b89464

Merge pull request #1951 from nuntipat/update-cv32e40p enjoy-digital 2024-05-14 12:11:50 +0200
9b6e231a1a

Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p enjoy-digital 2024-05-14 12:08:42 +0200
46911d5078 soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects). export_csr_c_rework Florent Kermarrec 2024-05-14 11:59:13 +0200
2574cc1ddc integration/export: Fix read_function refactoring. Florent Kermarrec 2024-05-14 11:55:34 +0200
7b7334fc17 cpu/vexiiriscv update Dolu1990 2024-05-14 11:41:21 +0200
29bb397bb6 soc/integration/export: Add parameter to enable/disable fields access function generation. Florent Kermarrec 2024-05-14 11:17:54 +0200
9f4bd5cec8 integration/export: Split get_csr_header in simpler functions. Florent Kermarrec 2024-05-14 11:00:41 +0200
c42cc350c6 integration/export: Split _get_rw_functions_c in simpler functions. Florent Kermarrec 2024-05-14 10:47:38 +0200
3506a5e82d cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working). Florent Kermarrec 2024-05-14 10:04:13 +0200
49897ee018 software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU. Florent Kermarrec 2024-05-14 10:02:56 +0200
b0acf6136e Fix CSR register definition for the CV32E41P core Nuntipat Narkthong 2024-05-13 18:15:51 -0400
41564cc47b Update CV32E40P to be based on the OpenHW Group's repo Nuntipat Narkthong 2024-05-13 16:03:23 -0400
2613ae606a interconnect/packet/Status: Simplify logic. Florent Kermarrec 2024-05-13 17:52:24 +0200
8b175c2575 CHANGES: Update. Florent Kermarrec 2024-05-13 16:33:11 +0200
0d3a8220dd

Merge pull request #1948 from Liamolucko/riscv-triples enjoy-digital 2024-05-07 15:15:09 +0200
b61e8b5d42

Merge pull request #1945 from Nicolas-Gaudin/master enjoy-digital 2024-05-07 15:13:44 +0200
e4cfe87109

Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert enjoy-digital 2024-05-07 15:10:55 +0200
903c5fb9a1 handle the case when AWVALID and WVALID are not asserted at the same clock cycle Alexey Morozov 2024-05-07 13:33:04 +0200
588b7a9519 Update Vexii Dolu1990 2024-05-06 19:48:56 +0200
86a43c9ff7 integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False. Florent Kermarrec 2024-05-06 14:59:17 +0200
e07c4fdb2a

Add missing 32-bit variants of RISC-V target triples Liam Murphy 2024-05-04 17:28:22 +1000
26f5e8a149 Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca for wishbobe. Dmitry Derevyanko 2024-05-03 00:51:01 +0300
56366ab5d6

Merge 1d7c738107 into 76a704377f AndrewD 2024-04-30 14:20:31 +0200
bd0adb5be7

Support isr for cv32e41p core Nicolas Gaudin 2024-04-30 14:07:07 +0200
bb2284b40b When part skipped do not threat it as sent Dmitry Derevyanko 2024-04-28 21:52:55 +0300
8d68c1ada3 If two clock already included in false path list then swapped tuple pair of clocks won't be added. Fix this by adding temporary variable with tuple Dmitry Derevyanko 2024-04-27 01:04:37 +0300
76a704377f

Merge pull request #1941 from motec-research/vexriscv_debug_halted enjoy-digital 2024-04-26 13:43:40 +0200
7aae2bf897

Merge pull request #1940 from enjoy-digital/Dolu1990-patch-1 Dolu1990 2024-04-26 11:21:18 +0200
fd477703db soc/integration/export: Revert #1938 (needs to be reviewed/discussed). Florent Kermarrec 2024-04-26 10:59:02 +0200
bd4ca4371d

Merge pull request #1938 from motec-research/guard_access_function AndrewD 2024-04-26 12:06:49 +1000
3a008b4988 cpu/vexriscv: expose o_halted Andrew Dennison 2024-04-26 10:29:45 +1000
ea33e37b1a

cpu/naxriscv update mBus to preserve memory accesses offset Dolu1990-patch-1 Dolu1990 2024-04-25 16:06:34 +0200
8831acba65 naxriscv fix simulation reset Dolu1990 2024-04-25 16:01:49 +0200
b6bfe42b6b

Merge pull request #1937 from motec-research/litex_term_deprecation_warning enjoy-digital 2024-04-25 11:38:09 +0200
ac1166946c

Merge pull request #1936 from motec-research/fix_recursive_exception enjoy-digital 2024-04-25 11:37:41 +0200
546f4d93ff

Merge pull request #1939 from hansfbaier/master Gwenhael Goavec-Merou 2024-04-25 07:03:44 +0200
d73190ac29 yosys+nextpnr: fix error message Hans Baier 2024-04-25 06:22:41 +0700
7481b1e161 soc/export: add guard for access_functions Andrew Dennison 2024-03-05 17:25:47 +1100
19db78da15 get_data_mod(): fix recursive exception reporting Andrew Dennison 2023-10-22 12:35:49 +1100
60d9a635ce tools/litex_term: fix DeprecationWarning Andrew Dennison 2024-02-19 14:32:54 +1100
1d7c738107 tools/litex_json2dts_linux: add *-endian to support csr ordering Andrew Dennison 2024-04-08 17:40:11 +1000
ab678b42f3 soc/integration: add csr ordering support Andrew Dennison 2024-04-08 17:40:11 +1000
d324c0e150 test/test_cpu: Disable Microwatt that seems to be broken. Florent Kermarrec 2024-04-20 08:51:10 +0200
e4dc68206d

Merge pull request #1932 from trabucayre/fix_openxc7 enjoy-digital 2024-04-19 13:43:31 +0200
7f7e44646d build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga) Gwenhael Goavec-Merou 2024-04-19 06:57:01 +0200
d6eeb20505 tools/litex_term: Minor cosmetic changes. Florent Kermarrec 2024-04-18 15:08:54 +0200
c343350551 Add bios disassembly file generation rules. Dmitry Derevyanko 2024-04-16 20:32:56 +0300
e00fe7df45 Use EventSourcePulse for fifo empty/full signals. Dmitry Derevyanko 2024-04-16 20:30:04 +0300
0c6ce1b313 Improve EventSource functions Dmitry Derevyanko 2024-04-16 20:25:56 +0300
22f4637570 Revert "Uart tx irq handling fix " (issue #554) Gwenhael Goavec-Merou 2024-04-16 14:01:38 +0200
3978af9c39 test/test_hyperbus: Update. Florent Kermarrec 2024-04-16 11:12:30 +0200
a44b7944ca CHANGES: Update. Florent Kermarrec 2024-04-16 10:51:19 +0200
fd6f913525 cores/hyperbus: Switch default latency_mode to variable. Florent Kermarrec 2024-04-16 10:19:59 +0200
62b9c64212 cores/hyperbus: Add status register to report configured latency_mode to software and allow corresponding configuration. Florent Kermarrec 2024-04-16 10:18:53 +0200
576ab24b6c

Merge pull request #1926 from enjoy-digital/hyperbus_variable_latency enjoy-digital 2024-04-15 17:39:04 +0200
e3d1391487

Merge pull request #1925 from chmousset/fix_efinix_t8q144 enjoy-digital 2024-04-15 17:38:37 +0200
ebabe82c70 software/bios/main: Rewrite HyperRAM init/config. hyperbus_variable_latency Florent Kermarrec 2024-04-15 16:03:55 +0200
67586e8a24 cores/hyperbus: Update docstring. Florent Kermarrec 2024-04-15 15:05:58 +0200
d25fd85f55 cores/hyperbus: More cleanups. Florent Kermarrec 2024-04-15 14:56:08 +0200
2100a6bd8c cores/hyperbus: reg_buf.source -> reg_ep. Florent Kermarrec 2024-04-15 14:48:38 +0200
1597791fb6 cores/hyperbus: Simplify reg_write/read_done. Florent Kermarrec 2024-04-15 14:43:15 +0200
8e48d0d330 cores/hyperbus: Cleanup/Improve Config/Reg Interfaces. Florent Kermarrec 2024-04-15 14:33:41 +0200
6e00cfa9d0 cores/hyperbus: Cleanup fixed/variable latency support. Florent Kermarrec 2024-04-15 14:05:39 +0200
739b66a15b

[fix] Trion T8 have a V1 PLL in BGA packages, but a V2 PLL in TQFP package. DP files varies accordingly Charles-Henri Mousset 2024-04-15 09:29:48 +0200
93f76ede95 bios/main: Test down to latency = 3, working. Florent Kermarrec 2024-04-15 12:06:49 +0200
a95f1b8486 cores/hyperbus: Make latency dynamically configurable. Florent Kermarrec 2024-04-15 12:06:11 +0200
6216bd4e99 cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation. Florent Kermarrec 2024-04-15 10:32:13 +0200
f62c9927d3 Fix for simultaneous interrupt and clear. Simplify a little bit Dmitry Derevyanko 2024-04-15 08:52:34 +0300
33a1fcda48 software/bios: Do minimal reconfiguration for variable latency and start testing latency cycles re-configuration. Florent Kermarrec 2024-04-12 19:35:31 +0200
f8c59c03e3 cores/hyperbus: Add variable latency support (working on ti60 f225). Florent Kermarrec 2024-04-12 18:50:19 +0200
b192103822 cores/hyperbus: Fix bytes order on register writes. Florent Kermarrec 2024-04-12 16:06:26 +0200
fb519ac260 test/test_hyperbus: Add test_hyperram_reg_write. Florent Kermarrec 2024-04-12 15:21:57 +0200
a32db7abad cores/hyperbus: Add with_csr parameter to make Register interface optional. Florent Kermarrec 2024-04-12 15:21:32 +0200
2d1dd45fd2

Merge pull request #1919 from nrndda/uart_tx_irq_handling_fix enjoy-digital 2024-04-12 10:45:12 +0200
2bc41928a3

Merge pull request #1916 from motec-research/spi_mmap enjoy-digital 2024-04-12 10:38:05 +0200
a891b2dd11

Merge pull request #1904 from machdyne/master enjoy-digital 2024-04-12 10:32:12 +0200
5d895bd3a7

Merge branch 'master' into master enjoy-digital 2024-04-12 10:32:05 +0200
441d05ee36 core/hyperbus: Start testing Register writes. Florent Kermarrec 2024-04-11 18:39:48 +0200
59756b4342 cores/hyperbus: Test and fix HyperRAM register read accesses. Florent Kermarrec 2024-04-11 18:29:48 +0200
2384d6fbd4 cores/hyperbus: Add initial HyperRAM Register access over CSRs. Florent Kermarrec 2024-04-11 17:51:47 +0200
b8ca87ece5 build/openocd: disabled 'poll off' because not supported by ECP5 Gwenhael Goavec-Merou 2024-04-11 15:13:52 +0200
62cf95c5da cpu/vexii add git Dolu1990 2024-04-10 12:21:47 +0200
555f89c22a set default l2 ways to 4 Dolu1990 2024-04-08 17:16:15 +0200
9654b40864 Got litex dma to work with vexii Dolu1990 2024-04-08 16:45:15 +0200
8f86108eed tools/litex_json2dts add vexiiriscv Dolu1990 2024-04-08 14:40:44 +0200
6885770e47 Uart tx irq handling fix Dmitry Derevyanko 2024-04-07 17:39:30 +0300
d3c46fb5dd Reset register for edge catching at the same time as pending register Dmitry Derevyanko 2024-04-07 16:13:55 +0300
3864615f6f tools/litex_json2dts_linux.py: improved cpu_isa_extension attribute (fdc) and fixed kernel panic during rocket booting with linux Gwenhael Goavec-Merou 2024-04-06 08:13:56 +0200