Tom Verbeure
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e9bbbb3965
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BarrielShifter -> BarrelShifter
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2018-06-03 07:40:11 +00:00 |
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Tom Verbeure
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0335543309
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More Unrolls
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2018-05-28 07:20:26 +00:00 |
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Tom Verbeure
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1613191779
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Unrool -> Unroll
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2018-05-28 07:18:13 +00:00 |
Dolu1990
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1752b5f184
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Give name to inter stages registers
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2018-05-27 23:39:49 +02:00 |
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Dolu1990
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c4f33b30e2
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Update SynthesisBench murax
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2018-05-24 14:03:28 +02:00 |
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Dolu1990
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4e7152ae5a
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IcestormFlow add ultraplus support
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2018-05-14 20:18:53 +02:00 |
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Dolu1990
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558af595a1
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Add ice40 synthesis results
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2018-04-26 13:14:37 +02:00 |
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Dolu1990
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bdcf3f6234
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Add HexTools and add a Briey main which load the ram
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2018-04-26 10:27:39 +02:00 |
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Dolu1990
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cfc324aa0f
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Allow csr mtvec to not have reset values
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2018-04-24 23:33:48 +02:00 |
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Dolu1990
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a9cbc48eb2
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PcManagerPlugin is can now handle an external reset vector signal
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2018-04-24 23:11:11 +02:00 |
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Dolu1990
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978eb9b6b2
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DBusCachedPlugin add CSR info
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2018-04-22 11:46:01 +02:00 |
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Dolu1990
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74f2a4194a
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Add ExternalInterruptArrayPlugin
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2018-04-20 17:56:21 +02:00 |
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Dolu1990
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6598e82920
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wishbone => word address, not byte address
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2018-04-19 11:22:06 +02:00 |
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Dolu1990
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455607b6b4
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Fix dBus IO access
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2018-04-18 14:11:59 +02:00 |
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Dolu1990
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6e59ddcc73
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Cached wishbone demo is passing regression tests
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2018-04-18 13:51:33 +02:00 |
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Dolu1990
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b37fc3fcc8
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Add VexRiscv Wishbone demo for sim (generation ok)
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2018-04-18 12:54:20 +02:00 |
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Dolu1990
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a66efcb35b
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Add wishbone support for i$ / d$ (not tested)
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2018-04-17 23:56:44 +02:00 |
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Dolu1990
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64022557bf
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
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2018-03-15 18:56:25 +01:00 |
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Dolu1990
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63c1b738ff
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
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2018-03-14 00:56:23 +01:00 |
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Dolu1990
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d9b7426cde
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undo InOutWrapper from Murax
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2018-03-14 00:47:23 +01:00 |
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Dolu1990
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91031f8d75
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DivPlugin is now based MulDivIterativePlugin (Smaller)
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2018-03-10 13:31:35 +01:00 |
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Dolu1990
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e437a1d44e
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Add division support in the MulDivInterativePlugin
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2018-03-09 22:41:47 +01:00 |
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Dolu1990
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36438bd306
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iterative mul improvments
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2018-03-09 20:00:50 +01:00 |
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Dolu1990
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674ab2c594
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experimental iterative mul/div combo
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2018-03-09 19:07:26 +01:00 |
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Dolu1990
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53970dd284
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SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
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2018-03-05 14:34:59 +01:00 |
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Dolu1990
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ccad64def5
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Pipeline CSR isWrite
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2018-02-26 10:19:33 +01:00 |
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Dolu1990
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2b6185b063
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Decoding logic : Add primes duplication removal
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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2b6f43cef8
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Fix Murax memory mapping range
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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5260ad5c35
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Decoding lib cleaning
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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d957934949
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Fix ICache exception priority over miss reload
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2018-02-19 22:44:46 +01:00 |
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Dolu1990
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d0e963559a
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Update readme with the new ICache implementation
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2018-02-18 23:48:11 +01:00 |
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Dolu1990
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93110d3b95
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Add jump priority managment in PcPlugins
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2018-02-16 14:27:20 +01:00 |
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Dolu1990
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506e0e3f60
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New faster/smaller/multi way instruction cache design.
Single or dual stage
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2018-02-16 02:21:08 +01:00 |
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Dolu1990
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3853e0313b
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SynthesisBench cleaning/experiments
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2018-02-11 14:53:42 +01:00 |
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Dolu1990
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0e6ae682b1
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Add architecture section describing plugins in the readme
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2018-02-09 00:44:27 +01:00 |
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Dolu1990
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57ebfee2e6
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Add more axi bridges
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2018-02-08 21:39:22 +01:00 |
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Dolu1990
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d4b05ea365
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Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
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2018-02-05 16:16:27 +01:00 |
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Dolu1990
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4729e46763
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Add DummyFencePlugin
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2018-02-03 12:28:53 +01:00 |
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Dolu1990
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f13dba847c
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Add custom csr gpio example
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2018-02-02 11:14:55 +01:00 |
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Dolu1990
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b7d8ed8a81
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Add onWrite/onRead/isWriting/isReading on the CsrPlugin
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2018-02-01 21:28:28 +01:00 |
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Dolu1990
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d2e5755df4
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revert removed code by mistake
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2018-01-31 18:29:30 +01:00 |
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Dolu1990
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30b05eaf96
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Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
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2018-01-31 18:13:42 +01:00 |
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Dolu1990
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bdbf6ecf17
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BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
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2018-01-29 14:52:31 +01:00 |
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Dolu1990
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0d318ab6b9
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Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
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2018-01-29 13:17:11 +01:00 |
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Dolu1990
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307c0b6bfa
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Now mret and ebreak are only allowed in CSR machine mode
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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26732942e5
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Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
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2018-01-25 01:11:57 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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9a89573942
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SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
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2018-01-06 22:09:42 +01:00 |
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Dolu1990
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43d3ffd685
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CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
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2018-01-04 17:37:23 +01:00 |
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Dolu1990
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611f2f487f
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Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
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2018-01-04 15:24:00 +01:00 |