Dolu1990
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b7d8ed8a81
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Add onWrite/onRead/isWriting/isReading on the CsrPlugin
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2018-02-01 21:28:28 +01:00 |
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Dolu1990
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4ee2482cbf
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Fix custom_csr regression against random ibus stall
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2018-01-31 18:33:21 +01:00 |
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Dolu1990
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d2e5755df4
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revert removed code by mistake
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2018-01-31 18:29:30 +01:00 |
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Dolu1990
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30b05eaf96
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Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
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2018-01-31 18:13:42 +01:00 |
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Dolu1990
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42e677ec0d
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1.40 DMIPS/Mhz update
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2018-01-29 15:24:14 +01:00 |
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Dolu1990
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bdbf6ecf17
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BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
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2018-01-29 14:52:31 +01:00 |
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Dolu1990
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0d318ab6b9
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Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
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2018-01-29 13:17:11 +01:00 |
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Dolu1990
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307c0b6bfa
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Now mret and ebreak are only allowed in CSR machine mode
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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93da5d29bc
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Fix dhrystone referance log
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2018-01-28 16:34:55 +01:00 |
Dolu1990
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3f9c8edc4c
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Update README.md
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2018-01-28 13:04:59 +01:00 |
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Dolu1990
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a98a0f72a6
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Update GCC information, update Murax performances
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2018-01-27 22:02:23 +01:00 |
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Dolu1990
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26732942e5
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Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
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2018-01-25 01:11:57 +01:00 |
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Dolu1990
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b3564e1b7e
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Fix Murax script flow (without rom file)
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2018-01-21 15:39:10 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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f5d5b91f7a
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More info about eclipse debugging
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2018-01-09 19:58:57 +01:00 |
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Dolu1990
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6a521a8d13
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Better MuraxSim gui
Add MuraxSim in the readme
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2018-01-09 08:59:17 +01:00 |
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Dolu1990
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9a89573942
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SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
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2018-01-06 22:09:42 +01:00 |
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Dolu1990
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43d3ffd685
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CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
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2018-01-04 17:37:23 +01:00 |
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Dolu1990
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2b7465e5df
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Add more atomic tests (PASS)
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2018-01-04 16:16:22 +01:00 |
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Dolu1990
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611f2f487f
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Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
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2018-01-04 15:24:00 +01:00 |
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Dolu1990
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4637e6cb48
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Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
add Atomic test flow
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2018-01-04 14:43:30 +01:00 |
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Dolu1990
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468dd3841e
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Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
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2018-01-04 13:16:40 +01:00 |
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Dolu1990
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4ed19f2cc5
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SpinalHDL 1.1.1
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2017-12-30 03:36:57 +01:00 |
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Dolu1990
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c3d950fb13
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Clean script folder
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2017-12-29 13:18:14 +01:00 |
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Dolu1990
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0d39e38906
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SpinalHDL 1.1.0
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2017-12-28 13:49:39 +01:00 |
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Dolu1990
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a4db278655
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Merge pull request #10 from Wallbraker/olimex
Port to iCE40HX8K-EVB
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2017-12-27 22:31:33 +01:00 |
Jakob Bornecrantz
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617a2948d0
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Port to iCE40HX8K-EVB
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2017-12-27 21:21:55 +00:00 |
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Dolu1990
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1b2476f217
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Update to sbt 0.13.16
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2017-12-24 18:20:02 +01:00 |
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Dolu1990
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3a913f0789
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SpinalHDL 1.0.5
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2017-12-22 23:18:34 +01:00 |
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Dolu1990
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3c0588eb4b
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remove MuraxSim fixed path
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2017-12-19 22:33:46 +01:00 |
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Dolu1990
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7f2b2181c1
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SpinalHDL 1.0.3
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2017-12-19 21:21:16 +01:00 |
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Dolu1990
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37849b7a66
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Spinal 1.0.2 sim update
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2017-12-19 00:40:52 +01:00 |
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Dolu1990
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15463a6276
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spinalhdl 1.0.1
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2017-12-17 19:36:18 +01:00 |
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Dolu1990
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f5a1793ef5
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Merge remote-tracking branch 'origin/sim'
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2017-12-17 17:57:51 +01:00 |
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Dolu1990
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ebda7526b5
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MuraxSim 1.0.0
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2017-12-17 17:57:09 +01:00 |
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Dolu1990
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dda5372a6c
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Fix typo
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2017-12-14 01:05:06 +01:00 |
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Dolu1990
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d6e0761065
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Fix led gui refresh rate
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2017-12-14 01:04:31 +01:00 |
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Dolu1990
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2259c9cb0f
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Add SpinalHDL sim (1.0.0)
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2017-12-14 00:57:12 +01:00 |
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Dolu1990
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5a8c131eb5
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Update README.md
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2017-12-13 13:24:43 +01:00 |
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Dolu1990
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5c8251d6a7
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Update README.md
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2017-12-13 13:23:55 +01:00 |
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Dolu1990
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04ca72df66
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Update README.md
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2017-12-05 16:29:26 +01:00 |
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Dolu1990
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f10dabd253
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SpinalHDL 0.11.5 update
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2017-12-05 15:58:05 +01:00 |
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Dolu1990
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e1b86ea511
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SpinalHDL 0.11.4 update
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2017-12-01 11:19:23 +01:00 |
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Dolu1990
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586d3ed286
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Update formal VexRiscv to halt on missaligned dbus
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2017-11-26 15:30:48 +01:00 |
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Dolu1990
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4de0aac469
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Merge branch 'formal'
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2017-11-24 14:03:25 +01:00 |
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Dolu1990
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b7f4f09814
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Update verilator makefiles to support the last SpinalHDL changes (process merges)
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2017-11-21 23:56:46 +01:00 |
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Dolu1990
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9b9bbaa4ad
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Add missing full config for the iBus
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2017-11-21 00:09:02 +01:00 |
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Dolu1990
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ce6fd6d0aa
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Add VexRiscvAxi4 demo
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2017-11-20 23:57:37 +01:00 |
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Dolu1990
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7c19288648
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Update Synthesis bench
Update some synthesis results
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2017-11-17 20:10:46 +01:00 |
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Dolu1990
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635417aec2
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Merge pull request #9 from kaofishy/master
Minor fixes to Murax.scala
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2017-11-16 21:16:53 +01:00 |