Charles Papon
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671aa5050e
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Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
Add MuraxConfig.fast
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2017-08-04 14:55:54 +02:00 |
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Charles Papon
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9f65a21f3e
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Readme add information about the Murax with a demo program in ROM
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2017-08-04 00:17:29 +02:00 |
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Charles Papon
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c033b32fc9
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scripts/murax remove jtag pullup which apparently break the functionality
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2017-08-03 23:59:48 +02:00 |
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Charles Papon
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d962406b26
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scripts/murax better makefile, add pullup on jtag interface
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2017-08-03 23:22:57 +02:00 |
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Charles Papon
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ac59eebb8d
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Add Murax configuration which integrate a boot programme :
Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
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2017-08-03 21:58:23 +02:00 |
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Dolu1990
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58981c0e8e
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Add Murax fast in synthesis bench
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2017-08-01 21:14:09 +02:00 |
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Charles Papon
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a37494f27f
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Set sbt organization to com.github.spinalhdl
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2017-08-01 20:43:15 +02:00 |
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Charles Papon
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a4d99d734b
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Typo fix
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2017-08-01 00:01:52 +02:00 |
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Charles Papon
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e3411012d7
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Add links to demo software
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2017-08-01 00:01:27 +02:00 |
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Charles Papon
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f44b345132
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Add console TX in the Murax verilator
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2017-07-31 21:04:41 +02:00 |
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Charles Papon
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fded0e7947
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Add MIT license
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2017-07-31 20:45:06 +02:00 |
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Charles Papon
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0c9a39d3ce
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Connect the UART interruption to the CPU
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2017-07-31 17:20:47 +02:00 |
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Charles Papon
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568c7d1365
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Update murax readme
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2017-07-31 13:57:34 +02:00 |
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Charles Papon
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c16a53c388
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Refractoring of some arbitration signals
Add UART into Murax
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2017-07-31 13:34:25 +02:00 |
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Dolu1990
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8708d2482f
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Add more information about dependencies
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2017-07-30 11:37:22 +02:00 |
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Charles Papon
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de33128e01
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Add Murax 0.55 DMIPS/Mhz
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2017-07-30 02:42:14 +02:00 |
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Charles Papon
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087e3dda89
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Add Murax scripts
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2017-07-29 22:43:43 +02:00 |
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Charles Papon
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2736681be6
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Add Murax in the readme
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2017-07-29 22:25:28 +02:00 |
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Charles Papon
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e8aa828744
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PcPlugin change fastPcCalculation into relaxedPcCalculation
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
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2017-07-29 21:36:30 +02:00 |
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Charles Papon
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3b66d986a8
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Fix cpu sending instruction memory request while being halted by the DebugPlugin
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2017-07-29 18:20:22 +02:00 |
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Charles Papon
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43253f61c1
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Update Murax info
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2017-07-29 02:52:57 +02:00 |
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Charles Papon
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fa887d3830
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Add pipelining option (hit 60 Mhz)
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2017-07-29 02:52:03 +02:00 |
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Charles Papon
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3bdf020c67
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Add interrupts and timer to Murax
8KB ram is the default now
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2017-07-29 01:59:17 +02:00 |
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Charles Papon
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823ac353ff
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Add Murax SoC (very light, work on ice40)
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2017-07-28 21:25:49 +02:00 |
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Dolu1990
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1450077b70
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Add Murax SoC (wip)
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2017-07-28 14:16:30 +02:00 |
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Charles Papon
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493f7721cb
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All FreeRTOS tests are now passing
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2017-07-28 00:07:51 +02:00 |
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Charles Papon
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800e9e79a5
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freertos regression now include O0 and O3 for rv32i and rv32im
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2017-07-27 01:23:50 +02:00 |
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Charles Papon
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6b3e2dbe7d
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Add FreeRTOS test regression (FREERTOS=yes)
Multithreaded regression
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2017-07-26 23:38:59 +02:00 |
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Charles Papon
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10d282b2ef
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Add DBusSimple early injection feature (better DMIPS)
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2017-07-26 23:36:25 +02:00 |
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Charles Papon
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6d117f5c81
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Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
freeRTOS pass
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2017-07-23 22:58:26 +02:00 |
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Charles Papon
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9fe4e1d54d
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Package refractoring VexRiscv -> vexriscv Plugin -> plugin
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2017-07-23 13:28:17 +02:00 |
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Charles Papon
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4b5bf7d807
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Briey Area down by 10% by spliting the memory system in two (System, Debug)
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2017-07-23 01:11:33 +02:00 |
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Charles Papon
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37c338ec98
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Avalon add read response support.
Fix debug instruction injection and IBusSimplePlugin interraction
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2017-07-21 20:39:54 +02:00 |
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Charles Papon
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54f785b1a3
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Add full avalon support (pass regression)
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2017-07-21 17:40:45 +02:00 |
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Charles Papon
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52f5020e64
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Rename some regression commands
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
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2017-07-21 14:32:49 +02:00 |
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Charles Papon
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575a410786
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Avalon regression (WIP)
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2017-07-20 14:20:19 +02:00 |
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Charles Papon
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570f0e1e3e
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D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax
|
2017-07-20 14:20:19 +02:00 |
|
Dolu1990
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950944e040
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typo fix
|
2017-07-19 18:36:30 +02:00 |
|
Dolu1990
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8643086fc0
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Add Briey area and timings into readme
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2017-07-19 18:34:16 +02:00 |
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Dolu1990
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02c9b0be75
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readme add full no cache
|
2017-07-17 16:52:36 +02:00 |
|
Charles Papon
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42e546ecd9
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Add fullNoMmuNoCache config
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2017-07-17 16:45:06 +02:00 |
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Dolu1990
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2b03b8487d
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Add Small and productive in readme
|
2017-07-17 15:38:52 +02:00 |
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Charles Papon
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fcec6cba86
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revert test changes
|
2017-07-17 15:26:37 +02:00 |
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Charles Papon
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617861ee6c
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Add smallAndProductive
|
2017-07-17 15:25:56 +02:00 |
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Charles Papon
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431750cac3
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readme update TOC
|
2017-07-17 14:22:13 +02:00 |
|
Charles Papon
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99c3397243
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readme, better plugin example
|
2017-07-17 14:19:28 +02:00 |
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Charles Papon
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84bba3adf0
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REG1/REG2 refractoring RS1/RS2
Add CustomeInstruction example
|
2017-07-17 14:02:56 +02:00 |
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Dolu1990
|
708a8f66de
|
typo fixes
|
2017-07-17 14:01:35 +02:00 |
|
Dolu1990
|
a4ac2ca8ce
|
Fix typo
|
2017-07-16 20:41:03 +02:00 |
|
Dolu1990
|
5190ba28e0
|
readme add features
|
2017-07-16 19:06:05 +02:00 |