Commit Graph

353 Commits

Author SHA1 Message Date
Dolu1990 6c673b0749
Merge pull request #27 from tomverbeure/typos
README language
2018-06-19 11:18:28 +02:00
Tom Verbeure 43ab18fb83 Unrool -> Unroll 2018-06-19 02:02:43 -07:00
Tom Verbeure 68cc141401 Language 2018-06-19 01:53:31 -07:00
Tom Verbeure dda9fe76e2 an -> a 2018-06-19 01:41:24 -07:00
Tom Verbeure 8d22f74c83 Language 2018-06-19 01:39:37 -07:00
Tom Verbeure 4e9e8b3e55 Language 2018-06-18 17:19:37 -07:00
Tom Verbeure 5c9c43aa00 Language 2018-06-18 17:09:29 -07:00
Dolu1990 d10bcbfbbb
Update README.md 2018-06-08 19:06:30 +02:00
Dolu1990 505a92916a
Update README.md 2018-06-08 18:00:22 +02:00
Dolu1990 4e73d4ff7d
Update README.md 2018-06-08 12:43:33 +02:00
Dolu1990 d9a049aa72
Update README.md 2018-06-08 12:31:55 +02:00
Dolu1990 cee3ad8147
Merge pull request #24 from tomverbeure/typos
Fix some missing Barriel -> barriel fixes
2018-06-04 11:09:05 +02:00
Tom Verbeure 52f1cdbca7 Fix some missing Barriel -> barriel fixes 2018-06-03 21:46:40 -07:00
Dolu1990 2f57b46edf
Merge pull request #23 from tomverbeure/typos
BarrielShifter -> BarrelShifter
2018-06-03 12:29:56 +02:00
Tom Verbeure e9bbbb3965 BarrielShifter -> BarrelShifter 2018-06-03 07:40:11 +00:00
Dolu1990 4a433e16f1
Merge pull request #21 from tomverbeure/typos
Typos...
2018-05-28 20:24:52 +02:00
Tom Verbeure 0335543309 More Unrolls 2018-05-28 07:20:26 +00:00
Tom Verbeure 1613191779 Unrool -> Unroll 2018-05-28 07:18:13 +00:00
Dolu1990 1752b5f184 Give name to inter stages registers 2018-05-27 23:39:49 +02:00
Dolu1990 c4f33b30e2 Update SynthesisBench murax 2018-05-24 14:03:28 +02:00
Dolu1990 6c47a3b2a3 update key 2018-05-17 19:07:58 +02:00
Dolu1990 e63e57981e travis test upload 2018-05-17 19:04:35 +02:00
Dolu1990 042962c1ae Fix travis 2018-05-17 18:56:31 +02:00
Dolu1990 938ed6abf6 Add bintraykey 2018-05-17 18:52:21 +02:00
Dolu1990 81790c32b8 Add travis 2018-05-17 18:43:52 +02:00
Dolu1990 4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990 558af595a1 Add ice40 synthesis results 2018-04-26 13:14:37 +02:00
Dolu1990 bdcf3f6234 Add HexTools and add a Briey main which load the ram 2018-04-26 10:27:39 +02:00
Dolu1990 cfc324aa0f Allow csr mtvec to not have reset values 2018-04-24 23:33:48 +02:00
Dolu1990 a9cbc48eb2 PcManagerPlugin is can now handle an external reset vector signal 2018-04-24 23:11:11 +02:00
Dolu1990 c7d852c497 Merge remote-tracking branch 'origin/Wishbone' 2018-04-22 12:15:25 +02:00
Dolu1990 978eb9b6b2 DBusCachedPlugin add CSR info 2018-04-22 11:46:01 +02:00
Dolu1990 74f2a4194a Add ExternalInterruptArrayPlugin 2018-04-20 17:56:21 +02:00
Dolu1990 6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990 455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990 6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990 b37fc3fcc8 Add VexRiscv Wishbone demo for sim (generation ok) 2018-04-18 12:54:20 +02:00
Dolu1990 a66efcb35b Add wishbone support for i$ / d$ (not tested) 2018-04-17 23:56:44 +02:00
Dolu1990 bd4d1eeb01 Update briey soc diagram 2018-03-24 13:49:50 +01:00
Dolu1990 925f6ae811
Update README.md 2018-03-22 15:25:40 +01:00
Dolu1990 cd4ffc2f3f
Update README.md 2018-03-22 15:24:56 +01:00
Dolu1990 7da85303dd
Update README.md 2018-03-22 14:40:08 +01:00
Dolu1990 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990 d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990 2f8f4d5444 SpinalHDL 1.1.5 2018-03-13 15:45:56 +01:00
Dolu1990 7ea3e24183 update readme perf 2018-03-10 18:37:38 +01:00
Dolu1990 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990 f133e69fed fix readme toc 2018-03-10 13:04:48 +01:00
Dolu1990 578e54376a Add MulDivIterativePlugin in readme 2018-03-10 12:57:42 +01:00