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VexRiscv
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676 Commits

Author SHA1 Message Date
Charles Papon 066f562c5e Got the MMU refilling itself with datacache cached memory access instead of io accesses 2019-04-03 14:32:21 +02:00
Charles Papon 8be40e637b #60 Got the new data cache design passing all tests and running linux 2019-04-02 23:44:53 +02:00
Charles Papon fd4da77084 #60 Got the new instruction cache design passing the standard regressions 2019-04-02 00:26:53 +02:00
Charles Papon bc0af02c97 #60 Got instruction cache running linux :D 2019-04-01 11:59:04 +02:00
Charles Papon 1dff9aff8a #60 Fix interrupt causing fetch privilege issues 2019-04-01 10:47:54 +02:00
Charles Papon e74a5a71eb Better simulation console integration 2019-04-01 10:31:55 +02:00
Charles Papon 369a3d0f5f #60 Sync everything, added much comment on the top of Linux.scala to help reproduce 2019-03-31 23:43:56 +02:00
Charles Papon c7314cc606 Got buildroot login, userspace, commands working 
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
 2019-03-31 15:17:45 +02:00
Dolu1990 de500ad8f9 Add qemu command 2019-03-30 18:29:17 +01:00
Dolu1990 9383445e0b Add a qemu option (wip) 2019-03-30 18:26:44 +01:00
Charles Papon 1a36f2689d #60 Fix software model. Forgot physical address for on RVC instruction 2019-03-30 11:24:29 +01:00
Charles Papon 29980016f3 #60 Fix instruction fetch exception PC by forcing LSB to be zero 2019-03-30 10:10:25 +01:00
Dolu1990 9fff419346 Better fix 2019-03-29 09:18:44 +01:00
Dolu1990 391cff69d3 #60 should fix the first instruction fetch privilege after interrupt 2019-03-29 09:02:44 +01:00
Dolu1990 0c48729611 Sync impact less changes (asfar i know) 2019-03-29 08:43:15 +01:00
Tom Verbeure 6038730e53 Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv 2019-03-27 19:49:09 -07:00
Dolu1990 9ac4998478 Fix emulator nested exception redirection privilege 2019-03-28 00:38:38 +01:00
Dolu1990 ac06111163 Fix MMU MPRV, Fix emulator nested exception 2019-03-27 22:58:30 +01:00
Dolu1990 0bed511a6c Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign 2019-03-27 18:58:02 +01:00
Dolu1990 43c3922a3d Add prerequired stuff 2019-03-27 10:55:20 +01:00
Dolu1990 f113946e66 Added a neutral LINUX_SOC for sim purposes 2019-03-27 10:53:41 +01:00
Dolu1990 b69c474fa2 #60 user space reached 
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
 2019-03-27 00:26:51 +01:00
Dolu1990 94fc2c3ecf Fix some models missmatch 
Add more SBI
Add hardware LR/SC support in dbus cacheless
 2019-03-26 01:25:18 +01:00
Dolu1990 1c3fd5c38b Fix mprv and add it into the softare model 2019-03-25 12:03:32 +01:00
Dolu1990 1ec11dc03d Fix mprv 2019-03-25 11:47:56 +01:00
Dolu1990 c34f5413a3 Add MMU MPRIV for easier machinemode emulation #60 2019-03-25 10:30:13 +01:00
Dolu1990 d63c6818df
Merge pull request #67 from tomverbeure/manual 
Some minor updated to the manual
 2019-03-25 02:07:42 +01:00
Dolu1990 9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Tom Verbeure 3d5e941aef Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv 2019-03-24 23:56:23 +00:00
Dolu1990 e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990 6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Dolu1990 d70f970b15
Merge pull request #66 from tomverbeure/IBusSimple_to_PipelinedMemoryBus 
Add getPipelinedMemoryBusConfig()
 2019-03-24 08:05:21 +01:00
Tom Verbeure ea62fd0e16 Same thing for DBusSimpleBus. 2019-03-23 23:36:13 +00:00
Tom Verbeure 1afad4f240 Ignore vim backup files. 2019-03-23 22:34:22 +00:00
Tom Verbeure 95c3e436dc Make toPipelinedMemoryBus() just like the other busses 2019-03-23 22:32:48 +00:00
Dolu1990 0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990 7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990 505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990 3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990 9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990 597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990 f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990 e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990 2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990 af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Tom Verbeure 59a2817e5c Update DecoderSimplePlugin manual. 2019-03-21 05:53:27 +00:00
Tom Verbeure 3f5605f22e Fix table. 2019-03-21 05:36:30 +00:00
Tom Verbeure 02a6312912 Update IBusCachedPlugin manual. 2019-03-21 05:34:15 +00:00
Tom Verbeure b7ddd02fc6 IBusSimplePlugin README. 2019-03-21 05:17:07 +00:00
Dolu1990 ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00