950944e040
typo fix
2017-07-19 18:36:30 +02:00
8643086fc0
Add Briey area and timings into readme
2017-07-19 18:34:16 +02:00
02c9b0be75
readme add full no cache
2017-07-17 16:52:36 +02:00
42e546ecd9
Add fullNoMmuNoCache config
2017-07-17 16:45:06 +02:00
2b03b8487d
Add Small and productive in readme
2017-07-17 15:38:52 +02:00
fcec6cba86
revert test changes
2017-07-17 15:26:37 +02:00
617861ee6c
Add smallAndProductive
2017-07-17 15:25:56 +02:00
431750cac3
readme update TOC
2017-07-17 14:22:13 +02:00
99c3397243
readme, better plugin example
2017-07-17 14:19:28 +02:00
84bba3adf0
REG1/REG2 refractoring RS1/RS2
...
Add CustomeInstruction example
2017-07-17 14:02:56 +02:00
708a8f66de
typo fixes
2017-07-17 14:01:35 +02:00
a4ac2ca8ce
Fix typo
2017-07-16 20:41:03 +02:00
5190ba28e0
readme add features
2017-07-16 19:06:05 +02:00
59e09ce269
Exclude TCL from the repo
2017-07-16 18:24:28 +02:00
a38b137db2
readme ToC fix
2017-07-16 18:10:03 +02:00
cd2fb402c1
readme ToC fix
2017-07-16 18:08:39 +02:00
3134725aa9
readme ToC fix
2017-07-16 18:06:45 +02:00
43ac85aaf6
Readme add index and demonstrator
2017-07-16 17:47:32 +02:00
8635054b38
cleaning
2017-07-16 14:42:24 +02:00
79c2972076
Update bench config with realistic embedded CSR
2017-07-16 14:34:42 +02:00
53300c4116
Add area and FMax in readme
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Add Synthesis bench
2017-07-16 13:50:19 +02:00
37ea699c55
Add Synthesis bench
2017-07-16 03:29:50 +02:00
6930e76042
Remove mepc from smallest CSR config
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Better readme
2017-07-16 00:44:23 +02:00
bc792a8655
Fix UartRx sim
2017-07-15 19:05:34 +02:00
74becb6633
Add VexRiscvAvalon QSysify
2017-07-15 09:41:39 +02:00
12d21a08e8
Add DebugPlugin avalon
2017-07-14 19:28:22 +02:00
d3dcfcec06
Add toAvalon bridge to cached bus
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Add VexRiscvAvalon demo
2017-07-14 18:04:41 +02:00
b9cbb27b81
Add Briey informations
2017-07-09 18:02:01 +02:00
f51f28164a
Fix info to flush data cache
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Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
2017-07-09 01:00:46 +02:00
8d34c04425
Fix CsrPlugin case issue
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Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
2017-06-27 19:37:46 +02:00
e9ab3d71d5
update readme
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add uart.elf binary for testing
2017-06-26 14:44:52 +02:00
4d7455f9c3
add retiming to the dataCache waysHit
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Add exception catches in the default briey configuration
2017-06-26 14:02:25 +02:00
e9e7cf9e7a
Add briey tracing
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Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
2017-06-24 14:09:12 +02:00
edf1b4ed5a
Cleaning, better jtag perf
2017-06-18 16:10:27 +02:00
a94343b98a
Update to SpinalHDL 0.10.14
2017-06-17 15:15:19 +02:00
c85f6b89de
Update verilator requirements
2017-06-15 20:27:20 +02:00
03be1f354f
Better readme
2017-06-15 14:06:32 +02:00
bc90331c49
Cleaning
2017-06-15 13:54:34 +02:00
88a2c4a603
Cleaning/Add documentation
2017-06-15 13:44:21 +02:00
835dd4ad50
Add CSR
2017-06-15 11:16:11 +02:00
f8678698fc
Briey improve AXI FMax
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Faster debugginPlugin regression
2017-06-11 11:52:59 +02:00
cbc770deb3
Improve TCP sockets latency
2017-06-10 19:38:42 +02:00
9b9d9e2582
Add Uart monitor in the briey testbench
2017-06-10 16:09:14 +02:00
11a63491bd
Add YAML feature to store CPU info
2017-06-09 16:06:18 +02:00
4b9668c063
Remove speed factor overriding when Trace
2017-06-09 08:41:12 +02:00
f46ec583d6
Briey is now working with DataCache on FPGA
2017-06-07 23:02:34 +02:00
8dcf5cf68a
Add missing import in Briey testbench
2017-06-07 16:56:29 +02:00
8da413dec3
Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK)
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Add SDRAM Verilator model
2017-06-07 04:19:35 +02:00
1e18daecc0
Add ICache and DCache axi bridges functions
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Add StaticMemoryTranslationPlugin
2017-06-01 17:54:56 +02:00
ac16558b6b
Add haltItByOther
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Axi4, remove some pipelining
2017-05-30 17:49:29 +02:00
Dolu1990