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Author SHA1 Message Date
Charles Papon
431750cac3 readme update TOC 2017-07-17 14:22:13 +02:00
Charles Papon
99c3397243 readme, better plugin example 2017-07-17 14:19:28 +02:00
Charles Papon
84bba3adf0 REG1/REG2 refractoring RS1/RS2 
Add CustomeInstruction example
 2017-07-17 14:02:56 +02:00
Dolu1990
708a8f66de typo fixes 2017-07-17 14:01:35 +02:00
Dolu1990
a4ac2ca8ce Fix typo 2017-07-16 20:41:03 +02:00
Dolu1990
5190ba28e0 readme add features 2017-07-16 19:06:05 +02:00
Dolu1990
59e09ce269 Exclude TCL from the repo 2017-07-16 18:24:28 +02:00
Dolu1990
a38b137db2 readme ToC fix 2017-07-16 18:10:03 +02:00
Dolu1990
cd2fb402c1 readme ToC fix 2017-07-16 18:08:39 +02:00
Dolu1990
3134725aa9 readme ToC fix 2017-07-16 18:06:45 +02:00
Dolu1990
43ac85aaf6 Readme add index and demonstrator 2017-07-16 17:47:32 +02:00
Dolu1990
8635054b38 cleaning 2017-07-16 14:42:24 +02:00
Dolu1990
79c2972076 Update bench config with realistic embedded CSR 2017-07-16 14:34:42 +02:00
Dolu1990
53300c4116 Add area and FMax in readme 
Add Synthesis bench
 2017-07-16 13:50:19 +02:00
Dolu1990
37ea699c55 Add Synthesis bench 2017-07-16 03:29:50 +02:00
Charles Papon
6930e76042 Remove mepc from smallest CSR config 
Better readme
 2017-07-16 00:44:23 +02:00
Charles Papon
bc792a8655 Fix UartRx sim 2017-07-15 19:05:34 +02:00
Charles Papon
74becb6633 Add VexRiscvAvalon QSysify 2017-07-15 09:41:39 +02:00
Charles Papon
12d21a08e8 Add DebugPlugin avalon 2017-07-14 19:28:22 +02:00
Charles Papon
d3dcfcec06 Add toAvalon bridge to cached bus 
Add VexRiscvAvalon demo
 2017-07-14 18:04:41 +02:00
Charles Papon
b9cbb27b81 Add Briey informations 2017-07-09 18:02:01 +02:00
Charles Papon
f51f28164a Fix info to flush data cache 
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
 2017-07-09 01:00:46 +02:00
Charles Papon
8d34c04425 Fix CsrPlugin case issue 
Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
 2017-06-27 19:37:46 +02:00
Charles Papon
e9ab3d71d5 update readme 
add uart.elf binary for testing
 2017-06-26 14:44:52 +02:00
Charles Papon
4d7455f9c3 add retiming to the dataCache waysHit 
Add exception catches in the default briey configuration
 2017-06-26 14:02:25 +02:00
Charles Papon
e9e7cf9e7a Add briey tracing 
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
 2017-06-24 14:09:12 +02:00
Charles Papon
edf1b4ed5a Cleaning, better jtag perf 2017-06-18 16:10:27 +02:00
Charles Papon
a94343b98a Update to SpinalHDL 0.10.14 2017-06-17 15:15:19 +02:00
Charles Papon
c85f6b89de Update verilator requirements 2017-06-15 20:27:20 +02:00
Charles Papon
03be1f354f Better readme 2017-06-15 14:06:32 +02:00
Charles Papon
bc90331c49 Cleaning 2017-06-15 13:54:34 +02:00
Charles Papon
88a2c4a603 Cleaning/Add documentation 2017-06-15 13:44:21 +02:00
Charles Papon
835dd4ad50 Add CSR 2017-06-15 11:16:11 +02:00
Charles Papon
f8678698fc Briey improve AXI FMax 
Faster debugginPlugin regression
 2017-06-11 11:52:59 +02:00
Charles Papon
cbc770deb3 Improve TCP sockets latency 2017-06-10 19:38:42 +02:00
Charles Papon
9b9d9e2582 Add Uart monitor in the briey testbench 2017-06-10 16:09:14 +02:00
Charles Papon
11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon
4b9668c063 Remove speed factor overriding when Trace 2017-06-09 08:41:12 +02:00
Charles Papon
f46ec583d6 Briey is now working with DataCache on FPGA 2017-06-07 23:02:34 +02:00
Dolu1990
8dcf5cf68a Add missing import in Briey testbench 2017-06-07 16:56:29 +02:00
Charles Papon
8da413dec3 Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK) 
Add SDRAM Verilator model
 2017-06-07 04:19:35 +02:00
Charles Papon
1e18daecc0 Add ICache and DCache axi bridges functions 
Add StaticMemoryTranslationPlugin
 2017-06-01 17:54:56 +02:00
Charles Papon
ac16558b6b Add haltItByOther 
Axi4, remove some pipelining
 2017-05-30 17:49:29 +02:00
Charles Papon
6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Charles Papon
213e154b40 Fix regression test debugPlugin bus 2017-05-28 17:41:09 +02:00
Charles Papon
8dddc7e334 GDB + openOCD successfully connect ! 2017-05-25 13:36:54 +02:00
Charles Papon
75f6b78daf OpenOCD successfuly connected to target 2017-05-24 23:53:31 +02:00
Charles Papon
1efed60307 Fix DebugPlugin 
Add DebugPlugin regression (PASS)
 2017-05-22 19:23:11 +02:00
Charles Papon
cc875d1c0b Add TCP server socket to manage debug access from openOCD (as instance) 2017-05-22 00:42:19 +02:00
Charles Papon
5cda2632df Start implementing debugPlugin test infrastructures 2017-05-21 23:50:40 +02:00