Hardware/VexRiscv
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689 commits

Author SHA1 Message Date
Charles Papon
c01c256757 Revert "Merge branch 'master' into dev" 
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
 2020-01-29 15:20:13 +01:00
Charles Papon
b5374433a5 Merge branch 'master' into dev 2020-01-29 12:50:41 +01:00
sebastien-riou
badc38d645 Merge remote-tracking branch 'origin/master' into arty 2020-01-17 00:54:19 +01:00
sebastien-riou
1fb1e358bb fix makefile clean target 2020-01-17 00:49:35 +01:00
sebastien-riou
97b2838d18 Murax on Digilent Arty A7-35 2020-01-16 21:58:55 +01:00
sebastien-riou
de9f704de2 better pin names in scala, bootloader without magic word 2020-01-13 21:58:08 +01:00
Charles Papon
f01da9c73b CsrPlugin add printCsr 2020-01-13 20:44:55 +01:00
sebastien-riou
b866dcb07f XIP on Murax improvements 2020-01-12 16:08:14 +01:00
Charles Papon
4c7025b964 Fix xtval when no exception and read_only 2020-01-06 20:07:23 +01:00
Charles Papon
2a06907902 fix compilation 2019-12-24 01:09:55 +01:00
Charles Papon
3b494e97cd Moved KeepAttribute to spinal.lib 2019-12-24 00:43:36 +01:00
Charles Papon
052c8dd602 Fix inWfi naming, fix regressions 2019-12-20 00:21:55 +01:00
Charles Papon
0702f97806 CsrPlugin add wfiOutput 2019-12-19 22:55:17 +01:00
Charles Papon
e25dfb4fbf CsrPlugin now make SATP write rescheduling the next instruction 2019-12-09 22:23:07 +01:00
Charles Papon
744b040c70 Sync CFU progress 2019-11-29 11:50:00 +01:00
Charles Papon
7ae218704e CsrPlugin now implement a IWake interface 
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
 2019-11-19 18:36:53 +01:00
Charles Papon
6d0d70364c Add BranchPlugin.decodeBranchSrc2 for branch target configs 2019-11-08 14:01:53 +01:00
Charles Papon
4fe7fa56c7 GenCustomInterrupt demo now enabled vectored interrupt 2019-11-07 19:55:26 +01:00
Charles Papon
bb405e705b Add UserInterruptPlugin 2019-11-07 19:52:45 +01:00
Charles Papon
8839f8a8e9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:45:24 +01:00
Charles Papon
2bf6a536c9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:44:09 +01:00
Charles Papon
bd2787b562 RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot 2019-11-01 16:24:07 +01:00
Charles Papon
bb9261773b Fix MulDiveIterative plugin when RSx have hazard in the execute stage 2019-10-23 00:02:08 +02:00
Charles Papon
67028cdb48 Add Mul16Plugin to regression tests 
Fix missing MulSimplePlugin in regressions tests
 2019-10-21 12:53:53 +02:00
Charles Papon
8091a872f3 Fix muldiv plugin for CPU configs without memory/writeback stages 2019-10-21 12:53:03 +02:00
Richard Petri
2d56c6738c Multiplication Plugin using 16-bit DSPs 2019-10-20 22:24:19 +02:00
Charles Papon
b4c75d4898 Merge remote-tracking branch 'origin/dev' into dev 2019-10-11 00:25:37 +02:00
Charles Papon
a2b49ae000 Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3 2019-10-11 00:25:22 +02:00
Charles Papon
310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon
711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon
3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon
51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon
5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register 
(used to inject instruction from the debug plugin)
 2019-10-03 00:20:33 +02:00
Charles Papon
49944643d2 Add regression for data cache without writeback stage, seem to pass tests, including linux ones 2019-09-23 15:20:51 +02:00
Charles Papon
bf82829e9e Data cache can now be used without writeback stage 2019-09-23 15:20:20 +02:00
Charles Papon
ace963b542 Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one 2019-09-21 14:13:28 +02:00
Charles Papon
e1795e59d5 Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages 2019-09-21 13:00:54 +02:00
Charles Papon
e8236dfebe Add MulSimplePlugin regressions 2019-09-21 12:49:46 +02:00
Sean Cross
b8b053e706 muldiviterative: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:36:01 +08:00
Sean Cross
fdc95debef dbuscached: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:49 +08:00
Sean Cross
0b79c637b6 mulsimpleplugin: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:23 +08:00
Charles Papon
6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon
d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon
5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990
6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Mateusz Holenko
86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Mateusz Holenko
8813e071bc Add litex target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00
Charles Papon
b65ef189eb sync with SpinalHDL SDRAM changes 2019-08-29 16:03:20 +02:00
Mateusz Holenko
5085877eed Fix handling LiteX uart and timer. 2019-07-24 16:09:21 +02:00
Mateusz Holenko
6a2584b840 Add litex target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-07-11 15:56:48 +02:00
Mateusz Holenko
39c3f408e5 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-07-11 15:50:15 +02:00
Mateusz Holenko
423355ecbf Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-07-11 14:09:06 +02:00
Mateusz Holenko
28a11976da Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-07-11 14:06:24 +02:00
Charles Papon
a2569e76c0 Update sdram ctrl package 2019-07-08 11:23:48 +02:00
Charles Papon
624c641af5 xip refractoring 2019-06-28 10:23:39 +02:00
Charles Papon
1257b056dc Revert "test only dynamic_target for intensive test" 
This reverts commit 635ef51f82.
 2019-06-16 18:24:59 +02:00
Charles Papon
635ef51f82 test only dynamic_target for intensive test 2019-06-16 17:43:07 +02:00
Charles Papon
9656604848 rework dynamic_target failure correction 2019-06-16 17:42:39 +02:00
Charles Papon
60c9c094a7 Merge remote-tracking branch 'origin/rework_jump_flush' into dev 2019-06-15 18:09:38 +02:00
Charles Papon
a3a0c402bc Remove broken freertos test and add zephyr instead 2019-06-15 10:46:10 +02:00
Charles Papon
617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch 2019-06-14 08:13:22 +02:00
Charles Papon
d603de1bfe Fix recent changes 2019-06-13 16:55:24 +02:00
Charles Papon
c8ab99cd0b Cleaning and remove BlockQ regression 2019-06-12 00:00:38 +02:00
Charles Papon
21ec368927 Fix DYNAMIC_TARGET by fixing decode PC updates 2019-06-11 19:56:33 +02:00
Charles Papon
afbf0ea777 Fix regression makefile 2019-06-11 01:05:49 +02:00
Charles Papon
066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests 2019-06-11 00:22:38 +02:00
Charles Papon
21c8933bbb Fix DYNAMIC_TARGET prediction correction in BranchPlugin 2019-06-11 00:12:29 +02:00
Charles Papon
5b53440d27 DYNAMIC_TARGET prediction datapath/control path are now splited 2019-06-10 22:20:32 +02:00
Charles Papon
0e95154869 individual regression : more env control 2019-06-10 21:01:41 +02:00
Charles Papon
bd46dd88aa Fix RVC fetcher pc branches 2019-06-10 20:48:04 +02:00
Charles Papon
24e1e3018c Fix exception handeling 2019-06-09 23:40:37 +02:00
Charles Papon
5243e46ffb Fix BranchPlugin when SRC can have hazard in execute stage 2019-06-09 20:15:36 +02:00
Charles Papon
af0755d8cf rework flush with flushNext and flushIt 
static branch prediction jump do not depend on stage fireing anymore
 2019-06-09 15:44:05 +02:00
Charles Papon
357681a5c6 csrPlugin add pipelinedInterrupt, set by default 2019-06-08 22:22:16 +02:00
Charles Papon
0df4ec45ad Merge remote-tracking branch 'origin/master' into dev 
# Conflicts:
#	build.sbt
 2019-06-05 00:35:41 +02:00
Charles Papon
56f7c27d18 Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege 2019-06-05 00:32:38 +02:00
Charles Papon
38a464a829 DataCache now allocate ways randomly 2019-05-25 00:28:30 +02:00
Charles Papon
4a40184b35 Add cache Bandwidth counter, previous commit was about random instruction cache way allocation 2019-05-25 00:22:27 +02:00
Charles Papon
94606d38e2 Add cache bandwidth counter 2019-05-25 00:21:48 +02:00
Charles Papon
206c7ca638 Fix Bmb datacache bridge 2019-05-24 00:22:58 +02:00
Charles Papon
f6f94ad7c1 Fix InstructionCache Bmb bridge 2019-05-22 19:03:26 +02:00
Charles Papon
9b49638654 Allow CsrPlugin config access 2019-05-22 17:27:47 +02:00
Charles Papon
8abc06c8f2 Add Bmb support for i$/d$ 2019-05-22 17:04:36 +02:00
Charles Papon
49b4b61a1a Update Bmb bridges 2019-05-20 14:14:42 +02:00
Charles Papon
0301ced000 Fix dBusSimplePlugin to bmb bridge 2019-05-16 19:49:13 +02:00
Charles Papon
3753f64429 Fix Bmb compilation 2019-05-13 23:44:20 +02:00
Dolu1990
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev 
Merge dev (SpinalHDL 1.3.4)
 2019-05-10 17:28:09 +02:00
Charles Papon
db307075cf Merge branch 'AHB' into dev 
# Conflicts:
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
 2019-05-07 17:21:52 +02:00
Charles Papon
01db217ab9 Add supervisor support in the ExternalInterruptArrayPlugin 2019-05-06 16:23:43 +02:00
Charles Papon
d27fa4766d DBusCachedPlugin add earlyWaysHits in regressions 2019-05-06 00:05:40 +02:00
Charles Papon
d12decde80 Remove test which had issues with the testbench ref checks because of getting passed delayed 2019-05-05 22:46:46 +02:00
Charles Papon
5f18705358 Add DBusCachedPlugin.relaxedMemoryTranslationRegister option 2019-05-05 21:19:48 +02:00
Charles Papon
c738246610 Remove the legacy pipelining from Axi4 cacheless bridges 2019-05-01 12:03:01 +02:00
Sean Cross
d1e215e312 caches: work without writeBack stage 
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.

Place the retry branch port into the correct stage.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-26 18:02:43 +08:00
Sean Cross
b2f387ccac MmuPlugin: fix generation without writeBack stage 
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.

Instead, pull from the most recent stage, which is where MMU access
should reside.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-26 18:01:35 +08:00
Charles Papon
d64589cc48 Add configs without memory/writeback stages in regressions 
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
 2019-04-25 17:36:13 +02:00
Charles Papon
74e5cc49f9 Add the linux config into the synthesis bench 2019-04-24 12:32:37 +02:00