Hardware/VexRiscv
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1083 commits 39 branches 2 tags 15 MiB
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344 commits

Author SHA1 Message Date
Dolu1990
a9d8c0a19f fpu wip 2021-01-18 11:38:26 +01:00
Dolu1990
3cda7c1f1b fpu wip 2021-01-15 14:03:37 +01:00
Dolu1990
04499c0b76 FPU sqrt functional 2021-01-14 18:33:24 +01:00
Dolu1990
85dd5dbf8e fpu div functional, sqrt wip 2021-01-14 15:56:56 +01:00
Dolu1990
8761d0d9ee FpuCore can add/mul/fma/store/load 2021-01-13 18:28:26 +01:00
Dolu1990
32f778613f DBusCachedPlugin now support asyncTagMemory 2020-07-08 01:36:58 +02:00
Dolu1990
a404078117 Few fixes 2020-07-05 13:16:39 +02:00
Dolu1990
c12f9a378d Fix inv regression 2020-06-20 13:18:46 +02:00
Dolu1990
685c914227 Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width 2020-05-12 23:59:38 +02:00
Dolu1990
0471c7ad76 Fix machineCsr test 2020-05-12 23:55:47 +02:00
Charles Papon
b592b0bff8 Add regression TRACE_SPORADIC, LINUX_SOC_SMP 
regression golden model now properly sync dut exceptions
 2020-05-09 17:00:13 +02:00
Dolu1990
0e76cf9ac8 i$ now support multi cycle MMU 2020-05-07 22:50:25 +02:00
Dolu1990
41ee8fd226 MmuPlugin now support multiple stages, D$ can now take advantage of that 2020-05-07 13:37:53 +02:00
Dolu1990
6323caf265 MMU now allow $ to match tag against tlb pyhsical values directly 
D$ retiming
D$ directTlbHit feature added for better timings
 2020-05-06 17:09:46 +02:00
Dolu1990
09724e907b play around with CSR synthesis impact on design size 2020-05-05 00:32:59 +02:00
Dolu1990
b0f7f37ac8 D$ now support memDataWidth > 32 2020-05-04 12:54:16 +02:00
Dolu1990
86e0cbc1f3 I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage 2020-04-29 13:59:43 +02:00
Dolu1990
eee9927baf IBusCachedPlugin now support memory data width multiple of 32 2020-04-28 22:10:56 +02:00
Dolu1990
03a0445775 Fix SMP for configuration without writeback stage. 
Include SMP core into the single core tests regressions
 2020-04-28 15:50:20 +02:00
Dolu1990
4a49b23636 Fix regression 2020-04-28 14:38:27 +02:00
Dolu1990
3885e52bb7 Merge remote-tracking branch 'origin/dev' into smp 2020-04-21 17:21:48 +02:00
Dolu1990
056bf63866 Add more consistancy tests 2020-04-21 16:03:03 +02:00
Dolu1990
b389878d23 Add smp consistency check, fix VexRiscv invalidation read during write hazard logic 2020-04-21 12:18:10 +02:00
Dolu1990
8c0e534c6b Add openSBI test, seem to work fine 2020-04-18 00:51:47 +02:00
Dolu1990
d5a52caab8 fix smp test barrier 2020-04-16 17:27:27 +02:00
Dolu1990
d88d04dbc4 More SMP tests (barrier via AMO and LRSC) 2020-04-16 15:23:25 +02:00
Dolu1990
fd52f9ba50 Add smp.bin 2020-04-16 02:22:18 +02:00
Dolu1990
73c21177e5 Add VexRiscvSmpCluster, seem to work on simple case 2020-04-16 01:30:03 +02:00
Dolu1990
b9ceabf128 few fixes 2020-04-16 01:29:13 +02:00
Dolu1990
a00605b10c fix Briey verilator 2020-04-13 13:01:12 +02:00
Dolu1990
467a2bc488 refactor DBus invalidation, and add invalidation enable 2020-04-11 19:06:22 +02:00
Dolu1990
abbfaf6bcf regression : restore normal invalidation setup 2020-04-10 18:58:03 +02:00
Dolu1990
0ad0f5ed3f Add d$ invalidation tests 
fix d$ invalidation, linux OK
 2020-04-10 14:28:16 +02:00
Dolu1990
296cb44bc4 Add hardware AMO support using LR/SC exclusive 2020-04-09 20:12:37 +02:00
Dolu1990
1d0e180e1d Add GenTwoStage config and UltraScale synthesis 2020-04-09 20:11:56 +02:00
Dolu1990
0c8ea4a368 DataCache add invalidation feature 2020-04-07 19:18:20 +02:00
Dolu1990
a52b833727 fix weird regression testbench memory bug 2020-04-06 21:42:44 +02:00
Dolu1990
a107e45116 fix non smp regression 2020-04-06 06:43:28 +02:00
Dolu1990
ca72a421be LrSc align software model to the hardware. Linux OK 2020-04-05 21:45:45 +02:00
Dolu1990
2eec18de65 LrSc SMP, linux crash in userspace 2020-04-05 16:28:46 +02:00
Dolu1990
c9bbf0d12a update LrSc reservation logic to match the spec 2020-04-04 21:21:35 +02:00
Dolu1990
2dac7dae32 Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction 2020-03-28 14:36:06 +01:00
Dolu1990
78d4660282 Merge branch 'dev' into rework_fetch 
# Conflicts:
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2020-03-01 22:58:25 +01:00
Dolu1990
ea5464ea26 TestIndividualFeatures is now multithreaded 2020-03-01 21:40:53 +01:00
Dolu1990
559260020b Improve testing infrastructure with more options and better readme 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
 2020-03-01 13:02:08 +01:00
Charles Papon
492310e6fa DBusCachedPlugin fix noWriteBack redo priority 2020-02-28 17:21:59 +01:00
Charles Papon
5ea0b57d1b Fix BRANCH_TARGET with RVC patch 2020-02-22 11:53:47 +01:00
Charles Papon
53a29e35e9 fix deleg external interrupt propagation time failure 2020-02-17 23:27:17 +01:00
Charles Papon
8be50b8e3d IBusFetcher now support proper iBusRsp.redo/flush 2020-02-17 12:50:12 +01:00
Charles Papon
5b8febb977 Revert "Revert "Merge branch 'master' into dev"" 
This reverts commit c01c256757.

Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
 2020-01-29 22:37:09 +01:00