Hardware/VexRiscv
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344 commits

Author SHA1 Message Date
Charles Papon
fd42e7701e Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala 2019-04-09 01:22:32 +02:00
Charles Papon
21cb8615fd Clean and fix things to get all the non-linux configs and machine only configs working 2019-04-08 16:06:05 +02:00
Charles Papon
ddf0f06834 Add more delegation tests 
Reduce dcache test duration
 2019-04-05 22:56:12 +02:00
Charles Papon
aeb418a99e Add dcache tests 2019-04-05 20:03:22 +02:00
Charles Papon
8459d423b8 add icache flush test 2019-04-05 18:11:33 +02:00
Charles Papon
8e6010fd71 Got the debug plugin working with the linux config (had to disable CSR ebreak) 2019-04-05 00:25:27 +02:00
Charles Papon
4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
 2019-04-04 20:34:35 +02:00
Charles Papon
8be40e637b #60 Got the new data cache design passing all tests and running linux 2019-04-02 23:44:53 +02:00
Charles Papon
fd4da77084 #60 Got the new instruction cache design passing the standard regressions 2019-04-02 00:26:53 +02:00
Charles Papon
bc0af02c97 #60 Got instruction cache running linux :D 2019-04-01 11:59:04 +02:00
Charles Papon
e74a5a71eb Better simulation console integration 2019-04-01 10:31:55 +02:00
Charles Papon
369a3d0f5f #60 Sync everything, added much comment on the top of Linux.scala to help reproduce 2019-03-31 23:43:56 +02:00
Charles Papon
c7314cc606 Got buildroot login, userspace, commands working 
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
 2019-03-31 15:17:45 +02:00
Charles Papon
1a36f2689d #60 Fix software model. Forgot physical address for on RVC instruction 2019-03-30 11:24:29 +01:00
Dolu1990
ad27007c3c DBusSimplePlugin AHB bridge add hazard checking, pass tests 2019-03-28 11:41:49 +01:00
Dolu1990
53c05c31c7 IBusSimplePlugin AHB bridge fix, pass tests 2019-03-28 10:12:42 +01:00
Dolu1990
9ac4998478 Fix emulator nested exception redirection privilege 2019-03-28 00:38:38 +01:00
Dolu1990
ac06111163 Fix MMU MPRV, Fix emulator nested exception 2019-03-27 22:58:30 +01:00
Dolu1990
f113946e66 Added a neutral LINUX_SOC for sim purposes 2019-03-27 10:53:41 +01:00
Dolu1990
b69c474fa2 #60 user space reached 
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
 2019-03-27 00:26:51 +01:00
Dolu1990
7a9f7c4fb9 Untested cacheless buses to AHB bridges 2019-03-26 16:30:53 +01:00
Dolu1990
94fc2c3ecf Fix some models missmatch 
Add more SBI
Add hardware LR/SC support in dbus cacheless
 2019-03-26 01:25:18 +01:00
Dolu1990
1c3fd5c38b Fix mprv and add it into the softare model 2019-03-25 12:03:32 +01:00
Dolu1990
9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990
e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990
6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Dolu1990
0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990
7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990
505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990
3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990
9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990
597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990
f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990
e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990
2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990
af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990
ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990
6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990
d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990
3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990
ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990
3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990
ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990
3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990
9a61ff8347 Merge remote-tracking branch 'origin/dev' 2019-03-10 11:14:09 +01:00
Dolu1990
56e3321394 cpp regresion now print the time of failure 2019-01-30 01:36:24 +01:00
Dolu1990
f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990
d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990
281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990
1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990
f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990
9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990
52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990
68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990
ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990
2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990
0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990
905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00
Dolu1990
f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990
0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990
594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990
c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990
8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990
0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990
48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990
c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990
0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990
7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990
aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990
1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990
86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990
ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990
b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990
d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990
791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990
0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Dolu1990
7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990
38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990
8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
 2018-08-17 20:56:51 +02:00
Dolu1990
1d3ac7830b restore tests without CSR catch all 2018-08-17 19:33:41 +02:00
Dolu1990
330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990
91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00
Dolu1990
32fe1dcbd4 Add google cloud VM regressions scripts 2018-07-07 21:47:09 +02:00
Dolu1990
3ea4f28354 wip 2018-07-07 11:39:42 +02:00
Dolu1990
9c1a8ea219 Fix EPC 
Fix Freertos binaries
wip
 2018-07-03 23:17:32 +02:00
Dolu1990
ffe5fa23f0 wip 2018-06-25 09:36:07 +02:00
Dolu1990
d73aa9ce00 rework csr exception/interrupt handeling wip 2018-06-24 00:14:55 +02:00
Dolu1990
8886f7e6d4 test wip 2018-06-19 16:15:42 +02:00
Dolu1990
1090111a6f TestIndividual is now fully random 2018-06-15 13:00:59 +02:00
Dolu1990
83864710a3 Fix IBusCached single cycle interaction with mmu bus 
Add random test configs
 2018-06-09 08:40:19 +02:00
Dolu1990
08a1212fca Add DBus simple/cached regressions 2018-06-07 02:31:18 +02:00
Dolu1990
6bc5431fcd Add iBusCached regressions 2018-06-07 00:57:26 +02:00
Dolu1990
5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990
7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00
Dolu1990
930563291c Allow RVC/dynamic_target/fetch bus latency > 1 all together 
Fix freeretos rvc regressions
 2018-06-05 02:21:05 +02:00
Tom Verbeure
52f1cdbca7 Fix some missing Barriel -> barriel fixes 2018-06-03 21:46:40 -07:00
Dolu1990
9f0387350b Add Freertos RVC binaries regression 2018-06-03 17:10:58 +02:00
Dolu1990
7375855e58 DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch) 2018-06-03 00:50:18 +02:00
Dolu1990
5943ee727e Fill travis, DhrystoneBench is now a Unit test 2018-05-28 09:02:01 +02:00
Dolu1990
9815763b7f Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
	src/test/cpp/regression/main.cpp
 2018-05-24 14:04:01 +02:00
Dolu1990
2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990
a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990
acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990
0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990
a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990
6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990
455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990
6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990
76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990
c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990
351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990
0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990
31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990
af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00
Dolu1990
1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990
ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990
5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990
9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990
5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990
137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990
d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990
93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990
506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990
3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990
d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990
b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990
4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990
30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990
bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990
0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990
93da5d29bc Fix dhrystone referance log 2018-01-28 16:34:55 +01:00
Dolu1990
26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990
3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990
6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990
43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure 2018-01-04 17:37:23 +01:00
Dolu1990
2b7465e5df Add more atomic tests (PASS) 2018-01-04 16:16:22 +01:00
Dolu1990
611f2f487f Fix DataCache atomic integration into DBusCachedPlugin 
Atomic is passing basic tests
 2018-01-04 15:24:00 +01:00
Dolu1990
4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. 
add Atomic test flow
 2018-01-04 14:43:30 +01:00
Dolu1990
468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer 2018-01-04 13:16:40 +01:00
Dolu1990
4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990
0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990
3c0588eb4b remove MuraxSim fixed path 2017-12-19 22:33:46 +01:00
Dolu1990
7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990
37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990
ebda7526b5 MuraxSim 1.0.0 2017-12-17 17:57:09 +01:00
Dolu1990
dda5372a6c Fix typo 2017-12-14 01:05:06 +01:00
Dolu1990
d6e0761065 Fix led gui refresh rate 2017-12-14 01:04:31 +01:00
Dolu1990
2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990
b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Ubuntu
008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00