Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity
1083 commits 39 branches 2 tags 15 MiB
Commit graph

344 commits

Author SHA1 Message Date
Dolu1990
2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990
a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990
acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990
0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990
a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990
6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990
455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990
6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990
76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990
c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990
351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990
0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990
31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990
af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00
Dolu1990
1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990
ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990
5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990
9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990
5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990
137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990
d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990
93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990
506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990
3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990
d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990
b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990
4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990
30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990
bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990
0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990
93da5d29bc Fix dhrystone referance log 2018-01-28 16:34:55 +01:00
Dolu1990
26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990
3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990
6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990
43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure 2018-01-04 17:37:23 +01:00
Dolu1990
2b7465e5df Add more atomic tests (PASS) 2018-01-04 16:16:22 +01:00
Dolu1990
611f2f487f Fix DataCache atomic integration into DBusCachedPlugin 
Atomic is passing basic tests
 2018-01-04 15:24:00 +01:00
Dolu1990
4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. 
add Atomic test flow
 2018-01-04 14:43:30 +01:00
Dolu1990
468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer 2018-01-04 13:16:40 +01:00
Dolu1990
4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990
0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990
3c0588eb4b remove MuraxSim fixed path 2017-12-19 22:33:46 +01:00
Dolu1990
7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990
37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990
ebda7526b5 MuraxSim 1.0.0 2017-12-17 17:57:09 +01:00
Dolu1990
dda5372a6c Fix typo 2017-12-14 01:05:06 +01:00
Dolu1990
d6e0761065 Fix led gui refresh rate 2017-12-14 01:04:31 +01:00
Dolu1990
2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990
b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Ubuntu
008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00
Dolu1990
aa859aae6b Update framework.h 
Add missing using namespace std;
 2017-10-05 10:08:09 +02:00
Dolu1990
8168c9bf3a Update simd_add makefile 2017-08-27 14:49:36 +02:00
Charles Papon
54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Charles Papon
f44b345132 Add console TX in the Murax verilator 2017-07-31 21:04:41 +02:00
Charles Papon
c16a53c388 Refractoring of some arbitration signals 
Add UART into Murax
 2017-07-31 13:34:25 +02:00
Charles Papon
e8aa828744 PcPlugin change fastPcCalculation into relaxedPcCalculation 
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
 2017-07-29 21:36:30 +02:00
Charles Papon
3b66d986a8 Fix cpu sending instruction memory request while being halted by the DebugPlugin 2017-07-29 18:20:22 +02:00
Charles Papon
fa887d3830 Add pipelining option (hit 60 Mhz) 2017-07-29 02:52:03 +02:00
Charles Papon
823ac353ff Add Murax SoC (very light, work on ice40) 2017-07-28 21:25:49 +02:00
Charles Papon
493f7721cb All FreeRTOS tests are now passing 2017-07-28 00:07:51 +02:00
Charles Papon
800e9e79a5 freertos regression now include O0 and O3 for rv32i and rv32im 2017-07-27 01:23:50 +02:00
Charles Papon
6b3e2dbe7d Add FreeRTOS test regression (FREERTOS=yes) 
Multithreaded regression
 2017-07-26 23:38:59 +02:00
Charles Papon
6d117f5c81 Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages) 
freeRTOS pass
 2017-07-23 22:58:26 +02:00
Charles Papon
4b5bf7d807 Briey Area down by 10% by spliting the memory system in two (System, Debug) 2017-07-23 01:11:33 +02:00
Charles Papon
37c338ec98 Avalon add read response support. 
Fix debug instruction injection and IBusSimplePlugin interraction
 2017-07-21 20:39:54 +02:00
Charles Papon
54f785b1a3 Add full avalon support (pass regression) 2017-07-21 17:40:45 +02:00
Charles Papon
52f5020e64 Rename some regression commands 
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
 2017-07-21 14:32:49 +02:00
Charles Papon
575a410786 Avalon regression (WIP) 2017-07-20 14:20:19 +02:00
Charles Papon
fcec6cba86 revert test changes 2017-07-17 15:26:37 +02:00
Charles Papon
617861ee6c Add smallAndProductive 2017-07-17 15:25:56 +02:00
Charles Papon
bc792a8655 Fix UartRx sim 2017-07-15 19:05:34 +02:00
Charles Papon
d3dcfcec06 Add toAvalon bridge to cached bus 
Add VexRiscvAvalon demo
 2017-07-14 18:04:41 +02:00
Charles Papon
f51f28164a Fix info to flush data cache 
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
 2017-07-09 01:00:46 +02:00
Charles Papon
e9ab3d71d5 update readme 
add uart.elf binary for testing
 2017-06-26 14:44:52 +02:00
Charles Papon
e9e7cf9e7a Add briey tracing 
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
 2017-06-24 14:09:12 +02:00
Charles Papon
edf1b4ed5a Cleaning, better jtag perf 2017-06-18 16:10:27 +02:00
Charles Papon
88a2c4a603 Cleaning/Add documentation 2017-06-15 13:44:21 +02:00
Charles Papon
f8678698fc Briey improve AXI FMax 
Faster debugginPlugin regression
 2017-06-11 11:52:59 +02:00
Charles Papon
cbc770deb3 Improve TCP sockets latency 2017-06-10 19:38:42 +02:00
Charles Papon
9b9d9e2582 Add Uart monitor in the briey testbench 2017-06-10 16:09:14 +02:00
Charles Papon
11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon
4b9668c063 Remove speed factor overriding when Trace 2017-06-09 08:41:12 +02:00
Charles Papon
f46ec583d6 Briey is now working with DataCache on FPGA 2017-06-07 23:02:34 +02:00
Dolu1990
8dcf5cf68a Add missing import in Briey testbench 2017-06-07 16:56:29 +02:00
Charles Papon
8da413dec3 Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK) 
Add SDRAM Verilator model
 2017-06-07 04:19:35 +02:00
Charles Papon
1e18daecc0 Add ICache and DCache axi bridges functions 
Add StaticMemoryTranslationPlugin
 2017-06-01 17:54:56 +02:00
Charles Papon
ac16558b6b Add haltItByOther 
Axi4, remove some pipelining
 2017-05-30 17:49:29 +02:00
Charles Papon
6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Charles Papon
213e154b40 Fix regression test debugPlugin bus 2017-05-28 17:41:09 +02:00
Charles Papon
8dddc7e334 GDB + openOCD successfully connect ! 2017-05-25 13:36:54 +02:00
Charles Papon
75f6b78daf OpenOCD successfuly connected to target 2017-05-24 23:53:31 +02:00
Charles Papon
1efed60307 Fix DebugPlugin 
Add DebugPlugin regression (PASS)
 2017-05-22 19:23:11 +02:00
Charles Papon
cc875d1c0b Add TCP server socket to manage debug access from openOCD (as instance) 2017-05-22 00:42:19 +02:00
Charles Papon
5cda2632df Start implementing debugPlugin test infrastructures 2017-05-21 23:50:40 +02:00
Charles Papon
9995c5109d move tests 2017-05-21 16:53:48 +02:00
Charles Papon
736478ff1d CsrPlugin now catch illegal CSR access (wrong address + to low privilege level) 2017-05-09 00:40:44 +02:00
Charles Papon
a51c27970b Add opcode for clean/invalidate the datacache 
Change mmu opcodes
 2017-05-07 16:02:55 +02:00
Charles Papon
4d6a6fbb02 Fix Instruction Data cache exceptions 
Pass all tests including CSR/FreeRTOS
 2017-05-07 12:51:47 +02:00
Charles Papon
ca1bc9cf69 DataCache plugin now support all exceptions 2017-05-07 10:44:41 +02:00
Charles Papon
534a4c3494 mmu working for instruction and data bus (both tested) 2017-05-03 18:42:54 +02:00
Charles Papon
2ed33106d6 MMU pass simple regression ! 2017-04-29 19:58:17 +02:00
Charles Papon
010ba568f0 MMU implemented 
Datacached using MMU implemented
It compile, but nothing is tested
 2017-04-28 16:41:23 +02:00
Charles Papon
ba2ca77114 Two stage datacache now pass dhrystone benchmark without error 2017-04-23 23:15:38 +02:00
Charles Papon
9040326273 WIP two stage DCache, nearly passed the dhrystone benchmark 2017-04-23 18:31:16 +02:00
Charles Papon
024e14ae58 Smaller and faster single stage instruction cache 
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
 2017-04-13 18:27:03 +02:00
Charles Papon
c83a157c64 IBusCachedPlugin with twoStage config is now compatible with syncronous regfile 2017-04-09 11:59:09 +02:00
Charles Papon
e3b9e671ec IBusCachedPlugin add two stage cache option for better FMax and better scaling 2017-04-08 17:42:13 +02:00
Charles Papon
efb27390a7 Better IntAluPlugin 
Better SrcPlugin
Better DBusCachedPlugin
 2017-04-06 01:28:52 +02:00
Charles Papon
179e7f7b4c IBusCachedPlugin add asyncTagMemory option 2017-04-05 14:25:11 +02:00
Charles Papon
2b24cbc8e1 Add pessimistic harzard options 
Add separated add/sum option in srcPlugin
 2017-04-04 00:25:39 +02:00
Charles Papon
8ff05bd2a8 Much better decoder using Quine-Mc Cluskey 2017-04-02 21:05:25 +02:00
Charles Papon
a9f7177181 Data cache pass dhrystone benchmark. 
Data cache todo -> bus error handling
 2017-04-01 17:06:59 +02:00
Charles Papon
2f384364d8 Data cache WIP 
refractoring
 2017-03-31 15:20:51 +02:00
Charles Papon
19fe998a52 Instruction cache is now able to catch bus errors 2017-03-30 17:34:24 +02:00
Charles Papon
95585b4d9a Add instruction cache plugin (tested) 2017-03-30 10:03:53 +02:00
Charles Papon
32d32845bd Add tests for iRsp, dRsp access faults 2017-03-28 20:25:58 +02:00
Charles Papon
62a55c4cf4 Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions 2017-03-28 01:24:29 +02:00
Charles Papon
eecc1e6b18 Add MachineCsr.mbadaddr logics 2017-03-27 18:35:27 +02:00
Charles Papon
91c52f4e46 Decoder now catch illegal instructions 2017-03-26 18:02:48 +02:00
Charles Papon
c5520656e5 Now able to catch missaligned instruction/data addresses 
Modify arbitration with an flushAll + isFlushed
 2017-03-26 17:20:07 +02:00
Charles Papon
4000191966 FreeRTOS tested 
removeIt no more colapse bubbles
 2017-03-25 16:44:42 +01:00
Charles Papon
9bbf3ee3e7 MachineCsr fix csr set/clear with zero 
MachineCsr pass external/timer interrupts test
 2017-03-24 17:40:37 +01:00
Charles Papon
72d65841d2 MachineCsr pass simple interrupt and exception tests 2017-03-23 23:12:44 +01:00
Charles Papon
94770f8e0b Add MachineCsr (untested) 2017-03-22 18:29:34 +01:00
Charles Papon
e9d3977737 Add Arbitration.flushIt 
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
 2017-03-21 18:40:50 +01:00
Charles Papon
c49373f3d1 Fix missing JAL, JALR encoding 2017-03-21 10:29:09 +01:00
Charles Papon
787682d4f6 Add comments 
Some refractoring
 2017-03-20 14:49:49 +01:00
Charles Papon
ecf853f491 Add Static/Dynamic branch prediction 2017-03-20 12:37:20 +01:00
Charles Papon
d569242124 Add Static branch prediction in decode stage 2017-03-19 23:27:35 +01:00
Charles Papon
88dee6d2bc Reduce area with reg[0] optimisation 2017-03-18 19:32:54 +01:00
Charles Papon
fc1bb7249a Add trace option to regresion 2017-03-18 14:06:42 +01:00
Charles Papon
5e9da0f27a Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
Charles Papon
31db6511dc Fix performance of removed instruction which halt were halting the pipeline 2017-03-18 10:51:55 +01:00
Charles Papon
20ca348707 Fix dCmd sent while the execute stage is removed 
Pass dhrystone benchmark without error !
 2017-03-17 21:26:42 +01:00
Charles Papon
7517ac797d Add MUL/DIV/REM support with plugins (pass Riscv-Tests) 2017-03-17 11:45:01 +01:00
Charles Papon
bf5bebda08 PcManager now drive PC asyncronously (use 1 cycle less in jump) 
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
 2017-03-15 21:10:44 +01:00
Charles Papon
c6610ea454 Fix halt arbitrations 2017-03-15 17:14:58 +01:00
Charles Papon
11797fbb6e Add sim performance print 2017-03-14 23:25:04 +01:00
Charles Papon
70d910e7d7 Load/Store pass Riscv-Tests 2017-03-14 23:00:24 +01:00
Charles Papon
7065ed5d93 All base instruction pass Riscv-Test (load/store not tested) 2017-03-14 20:13:35 +01:00
Charles Papon
ad6964f0bb Classify tests 
Riscv-test integration wip
 2017-03-14 00:42:48 +01:00
Charles Papon
df99a0d963 Better decoding 2017-03-13 18:30:37 +01:00
Charles Papon
e36c90af03 Add decoder bench 2017-03-13 16:17:57 +01:00
Charles Papon
9fc82c9736 Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00