d1e215e312
caches: work without writeBack stage
...
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.
Place the retry branch port into the correct stage.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:02:43 +08:00
b2f387ccac
MmuPlugin: fix generation without writeBack stage
...
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.
Instead, pull from the most recent stage, which is where MMU access
should reside.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:01:35 +08:00
6fc5406901
Merge branch 'linux'
2019-04-25 23:20:01 +02:00
0edc781b36
Add some coremark results
2019-04-25 23:18:45 +02:00
10255f2f81
Update readme
2019-04-25 21:11:23 +02:00
d64589cc48
Add configs without memory/writeback stages in regressions
...
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
431bec84fb
Switch to SpinalHDL 1.3.3 (release)
2019-04-24 22:17:46 +02:00
017e17f9fa
Update synthesis results in the readme
2019-04-24 12:32:57 +02:00
74e5cc49f9
Add the linux config into the synthesis bench
2019-04-24 12:32:37 +02:00
a331f35724
Icestorm flow now use nextpnr
2019-04-24 12:32:24 +02:00
b654d824ad
remove DebugPlugin from linux.scala, and set static branch prediction
2019-04-23 21:55:54 +02:00
266bdccc2e
update Riscv software model lrsc implementation
2019-04-23 21:55:54 +02:00
4078f84e8f
Dhrystone regression now also run coremark
2019-04-23 21:55:54 +02:00
c6dbaa52f6
Longer linux regression timeout for very slow configs
2019-04-21 22:16:42 +02:00
633e057d11
Split machine os regression in two smaller parts
2019-04-21 20:30:58 +02:00
14efe6ffda
Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes
2019-04-21 20:01:39 +02:00
d7ca153c8b
remove interrupt assertion
2019-04-21 19:45:24 +02:00
0e10c460c3
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
2019-04-21 17:58:42 +02:00
4cbb93cfc8
Look like zephyr mem_pool_threadsafe is a broken test
2019-04-21 17:48:08 +02:00
1c86bf7514
Increase liveness trigger to allow large instruction cache flush
2019-04-21 15:25:39 +02:00
4efa3b0d45
Update readme
2019-04-21 14:41:27 +02:00
d18dcc0540
Update regression.mk
...
reduce linux regression time a bit
2019-04-21 13:49:05 +02:00
fc4c078f17
Update regression.mk
...
Reduce machine os time
2019-04-21 13:36:25 +02:00
7e91b5e446
Fix travis
2019-04-21 12:55:01 +02:00
963805ad48
Bring freertos back in tests
...
Better travis test range
2019-04-21 12:50:28 +02:00
edde3e3011
Add zephyr tests
2019-04-21 02:56:44 +02:00
5cd74d2845
Merge remote-tracking branch 'origin/linuxDev' into linux
2019-04-20 15:33:30 +02:00
3b0f2e9551
better travis timings
...
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
2019-04-20 14:56:56 +02:00
06e63252e4
Merge branch 'linux' into linuxDev
2019-04-19 21:12:35 +02:00
b49076ecab
add missing coremark patch
2019-04-19 19:41:05 +02:00
ac5517f199
Travis : Bring back random regressions
2019-04-19 18:33:04 +02:00
728a5ff20f
Fix coremark binaries (no csr)
2019-04-19 18:28:46 +02:00
a496638c72
fix travis
2019-04-19 17:38:51 +02:00
e47b76fa67
#60 Added automated linux regression in travis
...
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
2019-04-19 17:35:48 +02:00
2810ff05b0
Fix emulator instruction emulation trap redirection to supervisor.
...
Impact only AMO less configs
2019-04-19 02:31:39 +02:00
b79b02152b
#60 Fix SFENCE_VMA deadlock
2019-04-18 18:33:06 +02:00
6f04c02cd2
TestInduvidualFeatures now use the linux config + MMU
2019-04-14 23:06:04 +02:00
8c7407967e
Fix non RVC fetcher exception PC capture
2019-04-14 23:04:30 +02:00
61d25e931e
#60 Add sim error message on RVC instruction without RVC capabilities
2019-04-13 10:44:06 +02:00
5d1ec604b2
Make regression sim great again
2019-04-13 10:41:15 +02:00
9ac1d3d59e
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
2019-04-13 10:40:53 +02:00
a12ca43284
README.md Update eclipse install
2019-04-12 17:41:15 +02:00
3301a1b364
Add CsrPlugin.userGen option which now remove privilegeReg when not set
2019-04-12 16:37:34 +02:00
d5723968da
Merge remote-tracking branch 'origin/master' into linux
...
# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
2019-04-12 16:26:08 +02:00
8421328ee1
restore freertos tests
2019-04-12 16:09:20 +02:00
13b774b535
#69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut
2019-04-12 15:56:22 +02:00
41ff87f83b
Remove jalr from decode branch prediction missaligned inibition
2019-04-12 15:27:10 +02:00
63cd5f42af
Fix #69 discoverd fmax issue with decode stage branch predictions
2019-04-12 15:24:33 +02:00
fdd2194c8f
Merge pull request #69 from tomverbeure/micro_warnings
...
GenMicro with warnings
2019-04-12 14:58:17 +02:00
b329ee85ad
#60 Fix missing ecallGen flag
2019-04-11 15:30:54 +02:00
Sean Cross
Dolu1990