Hardware/VexRiscv
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1052 commits 39 branches 2 tags 15 MiB
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693 commits

Author SHA1 Message Date
Dolu1990
41ee8fd226 MmuPlugin now support multiple stages, D$ can now take advantage of that 2020-05-07 13:37:53 +02:00
Dolu1990
8e025aeeaa more litex smp cluster pipelining 2020-05-07 13:18:11 +02:00
Dolu1990
fc0f3a2020 cleanup mmu interface 2020-05-06 18:05:20 +02:00
Dolu1990
6323caf265 MMU now allow $ to match tag against tlb pyhsical values directly 
D$ retiming
D$ directTlbHit feature added for better timings
 2020-05-06 17:09:46 +02:00
Dolu1990
ed4a89e4af more pipelineing in Litex SMP cluster interconnect 2020-05-06 17:06:45 +02:00
Dolu1990
8043feebd5 More VexRiscv smp cluster probes 2020-05-06 17:06:17 +02:00
Dolu1990
09724e907b play around with CSR synthesis impact on design size 2020-05-05 00:32:59 +02:00
Dolu1990
c16f2ed787 Add probes in SmpCluster sim 2020-05-04 12:54:28 +02:00
Dolu1990
b0f7f37ac8 D$ now support memDataWidth > 32 2020-05-04 12:54:16 +02:00
Dolu1990
93b386e16e litex smp cluster now use OO decoder 2020-05-02 23:44:58 +02:00
Dolu1990
f0745eb0d9 update SMP line size to 64 bytes 2020-05-02 23:44:27 +02:00
Dolu1990
09ac23b78f Fix SMP fence lock when 4 stages CPU 2020-05-01 12:45:16 +02:00
Dolu1990
f5f30615ba Got litex SMP cluster to work on FPGA 2020-05-01 11:14:52 +02:00
Dolu1990
dc0da9662a Update SMP fence (final) 2020-05-01 11:14:11 +02:00
Dolu1990
7c50fa6d55 SmpCluster now use i$ line of 64 bytes 2020-04-29 14:03:00 +02:00
Dolu1990
9e9d28bfa6 d$ now implement consistancy hazard by using writeback redo 2020-04-29 14:02:41 +02:00
Dolu1990
86e0cbc1f3 I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage 2020-04-29 13:59:43 +02:00
Dolu1990
7b80e1fc30 Set SMP workspace to use i$ memDataWidth of 128 bits 2020-04-28 22:11:41 +02:00
Dolu1990
eee9927baf IBusCachedPlugin now support memory data width multiple of 32 2020-04-28 22:10:56 +02:00
Dolu1990
03a0445775 Fix SMP for configuration without writeback stage. 
Include SMP core into the single core tests regressions
 2020-04-28 15:50:20 +02:00
Dolu1990
4a49b23636 Fix regression 2020-04-28 14:38:27 +02:00
Dolu1990
3ba509931c Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax 2020-04-27 17:38:06 +02:00
Dolu1990
5fd0b220cd CsrPlugin add openSbi config 2020-04-27 17:37:30 +02:00
Dolu1990
0c59dd9ed3 SMP fence now ensure ordering for all kinds of memory transfers 2020-04-27 17:37:15 +02:00
Dolu1990
3fb123a64a fix withStall 2020-04-21 21:20:54 +02:00
Dolu1990
3885e52bb7 Merge remote-tracking branch 'origin/dev' into smp 2020-04-21 17:21:48 +02:00
Dolu1990
056bf63866 Add more consistancy tests 2020-04-21 16:03:03 +02:00
Dolu1990
b389878d23 Add smp consistency check, fix VexRiscv invalidation read during write hazard logic 2020-04-21 12:18:10 +02:00
Dolu1990
0e55caacab deduplicae VexRiscv wishbone 2020-04-21 10:33:51 +02:00
Dolu1990
b383b4b98b Add commented usage of fromXilinxBscane2 2020-04-20 12:13:12 +02:00
Dolu1990
8e8b64feaa Got full linux / buildroot to boot in 4 cpu config 2020-04-19 19:49:26 +02:00
Dolu1990
a1b6353d6b workaround AMO LR/SC consistancy issue, but that need a proper fix 2020-04-19 19:48:57 +02:00
Dolu1990
ad2d2e411a Add tap less debug plugin bridges 2020-04-19 17:56:33 +02:00
Dolu1990
af128ec9eb revert to 4 cpu 2020-04-18 01:27:35 +02:00
Dolu1990
4a49e6d91f initialize the clint in sim 2020-04-18 01:26:31 +02:00
Dolu1990
befecc7ed6 cleaning 2020-04-18 00:51:57 +02:00
Dolu1990
8c0e534c6b Add openSBI test, seem to work fine 2020-04-18 00:51:47 +02:00
Dolu1990
d5a52caab8 fix smp test barrier 2020-04-16 17:27:27 +02:00
Dolu1990
d88d04dbc4 More SMP tests (barrier via AMO and LRSC) 2020-04-16 15:23:25 +02:00
Dolu1990
73c21177e5 Add VexRiscvSmpCluster, seem to work on simple case 2020-04-16 01:30:03 +02:00
Dolu1990
b9ceabf128 few fixes 2020-04-16 01:29:13 +02:00
Dolu1990
46207abbc4 dataCache now implement invalidation sync 2020-04-16 01:28:38 +02:00
Dolu1990
467a2bc488 refactor DBus invalidation, and add invalidation enable 2020-04-11 19:06:22 +02:00
Dolu1990
4a9b8c1f72 improve invalidation read during write hazard logic 2020-04-10 14:44:28 +02:00
Dolu1990
0ad0f5ed3f Add d$ invalidation tests 
fix d$ invalidation, linux OK
 2020-04-10 14:28:16 +02:00
Dolu1990
f71f360e32 Add SMP synthesis 2020-04-10 14:27:39 +02:00
Dolu1990
296cb44bc4 Add hardware AMO support using LR/SC exclusive 2020-04-09 20:12:37 +02:00
Dolu1990
1d0e180e1d Add GenTwoStage config and UltraScale synthesis 2020-04-09 20:11:56 +02:00
Dolu1990
861df664cf clean some AMO stuff 2020-04-08 18:48:01 +02:00
Dolu1990
6922f80a87 DataCache now implement fence operations 2020-04-08 18:12:13 +02:00
Dolu1990
9e1817a280 fix DataCache for config without invalidation 2020-04-07 20:05:24 +02:00
Dolu1990
0c8ea4a368 DataCache add invalidation feature 2020-04-07 19:18:20 +02:00
Dolu1990
1ef099e308 Merge branch 'dev' into smp 2020-04-07 12:29:58 +02:00
Dolu1990
f20eb4d541 Merge pull request #115 from antmicro/fix_emulator 
emulator: Use external hw/common.h from LiteX
 2020-04-07 12:29:40 +02:00
Dolu1990
5aa0b86d96 Fix DebugPlugin step by step 2020-04-07 12:13:40 +02:00
Dolu1990
2eec18de65 LrSc SMP, linux crash in userspace 2020-04-05 16:28:46 +02:00
Dolu1990
f2ef8e95ab Implement external LrSc 2020-04-05 11:38:57 +02:00
Dolu1990
ff074459ad Fix LrSc for configs without mmu 2020-04-04 22:54:35 +02:00
Dolu1990
c9bbf0d12a update LrSc reservation logic to match the spec 2020-04-04 21:21:35 +02:00
Dolu1990
2dac7dae32 Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction 2020-03-28 14:36:06 +01:00
Dolu1990
b3215e8beb Make things generated in a deterministic order 2020-03-24 13:11:07 +01:00
Dolu1990
defe3c5558 DataCache relax flush timings 2020-03-08 12:35:24 +01:00
Dolu1990
97db4f02a0 Merge branch 'rework_fetch' into dev 2020-03-07 18:22:46 +01:00
Dolu1990
44005ebf31 update Synthesis results 2020-03-07 18:22:01 +01:00
Charles Papon
58af94269e add CsrPlugin.csrOhDecoder 2020-03-05 00:13:04 +01:00
Charles Papon
505d0b700a MulDivPlugin now give names to div stages 2020-03-04 19:58:54 +01:00
Dolu1990
0a212c91fd update synthesisBench paths 2020-03-04 18:13:56 +01:00
Dolu1990
ff5cfc0dde Fix DebugPlugin step 2020-03-03 18:27:53 +01:00
Dolu1990
12463e40a4 improve debugPlugin step logic 2020-03-03 15:59:30 +01:00
Dolu1990
ef5398ce21 Fix #117 DataCache mem blackboxing 2020-03-02 14:24:27 +01:00
Dolu1990
54581f6d9e Fix #117 DataCache mem blackboxing 2020-03-02 14:23:59 +01:00
Charles Papon
25d880f6c7 Fix synthesis bench 2020-02-28 18:20:08 +01:00
Charles Papon
c94d8f1c6c Fetcher and IBusSimplePlugin flush reworked 2020-02-28 17:23:44 +01:00
Charles Papon
492310e6fa DBusCachedPlugin fix noWriteBack redo priority 2020-02-28 17:21:59 +01:00
Charles Papon
76d063f20a Fix MulPlugin keep attribute 2020-02-24 22:43:08 +01:00
Charles Papon
485b4a5838 Improve maxPerf configs 2020-02-23 23:52:43 +01:00
Charles Papon
fad09e805f Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns 2020-02-23 23:18:27 +01:00
Charles Papon
67d2071a32 typo 2020-02-23 23:17:02 +01:00
Charles Papon
c8016e90a4 MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP 2020-02-23 20:25:31 +01:00
Charles Papon
01e5112680 Fetcher RVC ensure redo keep PC(1) 
Fix BranchTarget RVC inibition
 2020-02-23 10:44:44 +01:00
Charles Papon
5ea0b57d1b Fix BRANCH_TARGET with RVC patch 2020-02-22 11:53:47 +01:00
Charles Papon
41008551c1 CsrPlugin redo interface do not need next pc calculation 2020-02-21 20:01:35 +01:00
Charles Papon
4ad1215873 Fix iBusSimplePlugin MMU integration 2020-02-21 13:28:42 +01:00
Charles Papon
befc54a444 No more Fetcher flush() API as it can now be done via the decoder.flushNext 2020-02-21 13:28:29 +01:00
Charles Papon
32fade50e5 Fix fetcher decompressor when driving decode stage 2020-02-21 02:03:29 +01:00
Charles Papon
59508d5b57 Fix target branch prediction for RVC, all default configs pass dhrystone 2020-02-20 02:27:57 +01:00
Charles Papon
a684d5e4d1 Rework/clean decompressor logic 2020-02-19 01:20:52 +01:00
Charles Papon
a7440426fd Fix FetchPlugin redo gen condition 
Fix injectorFailure reset
 2020-02-18 01:00:11 +01:00
Charles Papon
f63c4db469 Fix CsrPlugin pipeline liberator 2020-02-18 00:59:39 +01:00
Charles Papon
e0cd9a6e06 clean iBusRsp redo 2020-02-17 22:45:34 +01:00
Charles Papon
0e0a568743 Apply DYNAMIC_TARGET correction all the time 2020-02-17 21:43:02 +01:00
Charles Papon
e23295f06e Fix Fetcher pcValid pipeline 2020-02-17 19:29:41 +01:00
Charles Papon
9e75e2cb58 IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction. 
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
 2020-02-17 14:36:08 +01:00
Charles Papon
8be50b8e3d IBusFetcher now support proper iBusRsp.redo/flush 2020-02-17 12:50:12 +01:00
Charles Papon
ebfa9e6577 Merge branch 'dev' into rework_fetch 2020-02-16 18:52:31 +01:00
Charles Papon
29f85a7ae2 Remove INSTRUCTION_READY 
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
 2020-02-16 18:44:10 +01:00
Charles Papon
3d34d754a9 Remove usages of implicit string to B/U/S 2020-02-15 10:11:00 +01:00
Charles Papon
5b8febb977 Revert "Revert "Merge branch 'master' into dev"" 
This reverts commit c01c256757.

Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
 2020-01-29 22:37:09 +01:00
Charles Papon
c01c256757 Revert "Merge branch 'master' into dev" 
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
 2020-01-29 15:20:13 +01:00
Charles Papon
b5374433a5 Merge branch 'master' into dev 2020-01-29 12:50:41 +01:00