85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
64372d7876
targets/orangecrab: add spi-sdcard and workaround for ValentyUSB.
2020-06-11 19:21:44 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
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Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
45bd50b000
targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e).
2020-06-10 23:14:37 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
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Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b
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Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 23:07:33 +02:00
94861bbb9a
targets/orangecrab: uncomment MT41K512M16.
2020-06-10 19:30:07 +02:00
b6df166f5a
platforms/arty: add spisdcard to _sdcard_pmod_io.
2020-06-10 17:38:16 +02:00
00c8e40d02
platforms/ulx3s: add sdcard pins.
2020-06-10 17:37:50 +02:00
0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support
2020-06-10 03:20:32 +03:00
1acdb962a5
Add 5A-75E V7.1 board
2020-06-10 03:07:20 +03:00
939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 02:49:18 +03:00
485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:58 +01:00
e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:36 +01:00
f9a8edb973
targets/trellisboard: add initial LiteSDCard support
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-06-03 13:41:57 -04:00
d87a11a9cb
targets/pcie: use generate_litepcie_software on all targets with PCIe.
2020-06-03 08:30:54 +02:00
9f83b6e3cf
targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver.
2020-06-03 08:20:43 +02:00
091ec846a1
targets/acorn_cle_215: automatically copy software from litepcie and generate headers in kernel directory.
2020-06-02 20:09:45 +02:00
06edf48897
targets: rename gateware-toolchain parameter to toolchain.
2020-06-02 13:45:05 +02:00
0b11aba8a1
platforms/nexys_video: add spisdcard pins.
2020-05-29 19:37:04 +02:00
76df4e39c8
targets: simplify Ethernet/Etherbone integration on targets with both.
2020-05-29 19:20:27 +02:00
2e1a816d1f
pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
2020-05-29 10:41:35 +02:00
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read
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ZCU104: add I2C
2020-05-27 14:56:31 +02:00
e5578a1ae8
zcu104/platform: change I2C number to 0
2020-05-27 14:31:22 +02:00
ac1f1cd6a7
zcu104: add I2C
2020-05-27 12:47:43 +02:00
71f220a24d
colorlight_5a_75b: remove unnecessary parenthesis.
2020-05-27 10:13:44 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
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Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
d6518c7dc2
prog/openocd: fix openocd_xc6 cfgs.
2020-05-27 08:48:16 +02:00
22f18f618e
pano_logic_g2: move gmii_rst_n to _CRG.
2020-05-26 08:36:06 +02:00
0648c04158
Updated comment, added link to clocking documentation.
2020-05-25 14:48:24 -07:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
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Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
435913f7d8
platforms/nexys4ddr: add option to build with spi-mode sdcard support
2020-05-24 19:09:25 -04:00
0d549a8c89
platforms: add forest_kitten_33 initial platform suppport.
2020-05-24 11:22:02 +02:00
12b54a7a7f
platforms/alveo_u250: add clk300 clock constraints.
2020-05-24 11:18:30 +02:00
46f78b5002
nexys_video: add usb_fifo pins.
2020-05-22 14:28:55 +02:00
445338e2e7
platforms/nexys_video: add specific openocd cfg (use channel 1).
2020-05-22 14:12:45 +02:00
5aeb7d85e6
targets/acorn_cle_215: fix typo in description.
2020-05-21 10:18:06 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
76551dec4c
platforms/nexys_video: add sdcard pins, move clk/rst to top.
2020-05-20 13:05:18 +02:00
83457b8791
platforms/arty: add _sdcard_pmod_io.
2020-05-20 12:09:43 +02:00
8158d94ae7
targets/c10lprefkit: switch to litehyperbus.
2020-05-19 15:48:19 +02:00
587caf7584
paltforms/marblemini: add break_off_pmod.
2020-05-19 15:42:53 +02:00
c2cd863658
platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash.
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The Platform file should not contain import code related to cores, this has to be done in the target.
2020-05-19 15:29:25 +02:00
3f0f12011b
Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params
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ECP5-EVN SpiFlash parameters
2020-05-19 15:16:25 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
c0b7afc739
targets/alveo_u250: +x.
2020-05-16 11:13:01 +02:00
67d2a4940e
tools/extract_xdc_pins: +x.
2020-05-16 11:12:46 +02:00
482d7a6b95
targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations.
2020-05-14 15:34:00 +02:00
2bb7fce5e3
targets/acorn_cle_215: add minimal instructions to reproduce the results.
2020-05-13 17:55:52 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
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[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
c7404e356f
targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury).
2020-05-09 16:39:17 +02:00
d05b10fd76
target/camlink_4k: add missing import.
2020-05-09 12:27:07 +02:00
4faa91c7f2
platforms/marblemini: review/cleanup.
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- add copyrights.
- add link to documentation.
- reindent code.
- rename some IOs (for consistency with the others platforms).
- add pullup on clk20_vcxo_en.
- set clk20_vcxo as default clock.
- remove ununnecessary eth constraints. (we are using IO primitives).
- move PMODS to connectors (for consistency with others platforms).
2020-05-09 10:16:42 +02:00
4ffdcb5ea9
Merge pull request #75 from jersey99/marblemini
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Marblemini [https://github.com/berkeleylab/marble-mini/ ]
2020-05-09 09:39:40 +02:00
e4ccfcfad1
platforms/marblemini.py: Cleanup. Add openocd for programming marblemini
2020-05-08 17:20:14 -07:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
b9a0f2363c
Merge pull request #74 from tommythorn/master
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targets/orangecrab.py: propagate command arguments
2020-05-08 07:28:05 +02:00
a7d6de78ae
Merge branch 'master' into marblemini
2020-05-07 12:19:47 -07:00
5f7f087cba
community/platforms/marblemini.py: Added marblemini from https://github.com/berkeleylab/marble-mini/
2020-05-07 12:17:42 -07:00
19b12fd984
targets/panol_logic_g2: replace with a minimal target.
2020-05-07 16:36:04 +02:00
99c04358bf
platforms/pano_logic_g2: simplify/cleanup.
2020-05-07 16:35:34 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
27c242b2ca
targets/pcie: switch to PCIe X4 on all boards that support it.
2020-05-07 12:18:39 +02:00
f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
6335717eca
targets/orangecrab.py: propagate command arguments
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The parsed args are stripped off by soc_core_argdict() (called from
soc_sdram_argdict() so we have to pass them explicitly (or pass the
original "args", but this mimics the rest of the code in the repo).
This fixes #72
2020-05-06 18:24:11 -07:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
117d1a1c75
prog: add colorlight_5a_75b openocd config.
2020-05-06 16:01:59 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
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Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
86648ec7d8
platforms/vcu118: rename ddram_second_channel to ddram:1.
2020-05-05 09:54:11 +02:00
e1820c7831
platforms/ac701: indent HPC.
2020-05-05 09:49:59 +02:00
2129b67779
platforms: make sure all plarforms have separators.
2020-05-05 09:47:55 +02:00
ea0eda9f75
platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series.
2020-05-05 09:42:34 +02:00
588bbac719
add prog directory with some Xilinx OpenOCD configurations files.
2020-05-05 09:11:06 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
...
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
088cceca8b
Add Alveo U250 platform and target
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
0ba8045789
Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H
2020-04-28 21:56:33 +02:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4ad6042e07
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:36:18 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
...
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
Florent Kermarrec
Vadim Kaushan
rob-ng15
Gabriel Somlo
Jędrzej Boczar
Skip Hansen
Vamsi K Vytla
Tommy Thorn
David Shah
Ilya Epifanov
Dave Marples