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Author SHA1 Message Date
Sebastien Bourdeauducq
c1041b9a5f simplebus: export GetSigName function 2011-12-08 23:06:04 +01:00
Sebastien Bourdeauducq
b2bc5ad4f4 corelogic: multimux module 2011-12-08 23:04:34 +01:00
Sebastien Bourdeauducq
b0c5b74c22 verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq
512655c108 fhdl: improve automatic signal naming 2011-12-08 21:28:20 +01:00
Sebastien Bourdeauducq
5034af3038 Corelogic conversion example 2011-12-08 21:25:05 +01:00
Sebastien Bourdeauducq
62f70a54f0 corelogic: MC divider module 2011-12-08 21:19:40 +01:00
Sebastien Bourdeauducq
84eb964adc fhdl: support negation operator 2011-12-08 21:15:44 +01:00
Sebastien Bourdeauducq
bf021efa2b verilog: fix unary operator conversion 2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq
78f18ad593 corelogic: round-robin module 2011-12-08 21:15:02 +01:00
Sebastien Bourdeauducq
7c99e51b90 Named buses 2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq
5720a51dad wishbone: add missing SEL 2011-12-08 19:09:32 +01:00
Sebastien Bourdeauducq
ed05ec5f6a instances: signal override 2011-12-08 18:56:14 +01:00
Sebastien Bourdeauducq
c43f3da534 Wishbone declarations 2011-12-08 18:47:41 +01:00
Sebastien Bourdeauducq
a6b86168ce Simple bus base class 2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq
1b637cea61 Instance support 2011-12-08 16:35:32 +01:00
Sebastien Bourdeauducq
fab02f84cb fhdl: fix implicit slice index 2011-12-07 22:21:30 +01:00
Sebastien Bourdeauducq
82f77180d5 fhdl: cleanup value bv 2011-12-07 22:21:10 +01:00
Sebastien Bourdeauducq
0e8d894a35 Variable conversion 2011-12-05 22:00:06 +01:00
Sebastien Bourdeauducq
4340680704 Cleanup 2011-12-05 19:25:32 +01:00
Sebastien Bourdeauducq
ec51f09c98 Case support + register bank generator 2011-12-05 17:43:56 +01:00
Sebastien Bourdeauducq
458cfc8623 CSR bus definitions 2011-12-05 00:16:44 +01:00
Sebastien Bourdeauducq
5acf2e169f Examples folder 2011-12-04 23:39:48 +01:00
Sebastien Bourdeauducq
e099f4d52f Reset insertion 2011-12-04 22:41:50 +01:00
Sebastien Bourdeauducq
cd8544c758 Verilog generator 2011-12-04 22:26:32 +01:00
Sebastien Bourdeauducq
499b95a519 Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00