Sebastien Bourdeauducq
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5208baada8
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bus/wishbone/SRAM: support init and read_only
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2013-05-19 20:53:54 +02:00 |
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Sebastien Bourdeauducq
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29b468529f
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bus: replace simple bus module with new bidirectional Record
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2013-04-01 21:54:21 +02:00 |
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Sebastien Bourdeauducq
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51bec340ab
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sim: remove PureSimulable (superseded by Module)
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2013-03-15 19:41:30 +01:00 |
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Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
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Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
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Sebastien Bourdeauducq
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3fae6c8f03
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Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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280a87ea69
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elsewhere: do not create interface in default param
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2012-12-06 17:34:48 +01:00 |
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Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
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Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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ece786d6aa
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bus/wishbone: allow specifying existing interface
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2012-11-17 19:42:06 +01:00 |
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Sebastien Bourdeauducq
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8de192dfbd
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x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
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Sebastien Bourdeauducq
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b4613d913f
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bus/wishbone: remove use of deprecated multimux
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2012-07-13 17:17:20 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
|
PureSimulable
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2012-06-12 17:08:56 +02:00 |
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Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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f061b25a24
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bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
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Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
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Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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a99c2acfa8
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Remove explicit bus names and rely on the new automatic namer
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2012-01-27 22:20:57 +01:00 |
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Sebastien Bourdeauducq
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076c171c7b
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Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
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Sebastien Bourdeauducq
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20425703fa
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Wishbone: omit fixed LSBs
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2012-01-13 17:29:05 +01:00 |
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Sebastien Bourdeauducq
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ba40f58491
|
corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
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Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
|
fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
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39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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92f24b784d
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wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
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923fc52e68
|
wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
|
4d1a960308
|
wishbone: decoder + shared bus interconnect
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2011-12-09 13:11:52 +01:00 |
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Sebastien Bourdeauducq
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5c7131dc86
|
wishbone: arbiter
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2011-12-08 23:21:25 +01:00 |
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Sebastien Bourdeauducq
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7c99e51b90
|
Named buses
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2011-12-08 19:16:08 +01:00 |
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Sebastien Bourdeauducq
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5720a51dad
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wishbone: add missing SEL
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2011-12-08 19:09:32 +01:00 |
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Sebastien Bourdeauducq
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c43f3da534
|
Wishbone declarations
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2011-12-08 18:47:41 +01:00 |