Sebastien Bourdeauducq
|
603a4ef51e
|
liteeth: adapt to new ModuleTransformer
|
2015-04-10 11:42:25 +08:00 |
Florent Kermarrec
|
ea613cd8ee
|
litesata: update build core target generation
|
2015-04-09 00:00:25 +02:00 |
|
Florent Kermarrec
|
03aa972bb6
|
lite*: finish ModuleTransformer adaptations (need to be tested on board)
|
2015-04-08 23:27:22 +02:00 |
|
Sebastien Bourdeauducq
|
3a2b677f85
|
soc,cpuif: support user defined constants
|
2015-04-09 00:34:36 +08:00 |
|
Sebastien Bourdeauducq
|
176b9240a9
|
soc: use new ModuleTransformer API
|
2015-04-06 23:52:34 +08:00 |
Robert Jordens
|
66f8dcbfaf
|
lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
|
2015-04-04 19:17:24 +08:00 |
|
Florent Kermarrec
|
2583e975f0
|
soc/cpuif: fix CSR base generation for memories (name is already fullname)
|
2015-04-03 13:57:37 +02:00 |
|
Florent Kermarrec
|
c9c11e7aa8
|
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
|
2015-04-03 12:45:32 +02:00 |
|
Sebastien Bourdeauducq
|
85b3cced22
|
use str.format
|
2015-04-03 17:43:46 +08:00 |
|
Florent Kermarrec
|
0db6e1d624
|
soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
|
2015-04-03 11:14:28 +02:00 |
|
Florent Kermarrec
|
b437dc3185
|
remove use of _r prefix on CSRs
|
2015-04-02 12:18:43 +02:00 |
|
Sebastien Bourdeauducq
|
696819cc7f
|
move gpio from cpu.peripherals to com
|
2015-04-02 17:17:33 +08:00 |
|
Sebastien Bourdeauducq
|
382ed013af
|
minor cleanups
|
2015-04-02 14:40:29 +08:00 |
|
Sebastien Bourdeauducq
|
bbdbf87599
|
Merge branch 'master' of github.com:m-labs/misoc
|
2015-04-02 10:14:24 +08:00 |
|
Florent Kermarrec
|
60124be293
|
adapt LiteSATA to new SoC
|
2015-04-01 22:52:19 +02:00 |
|
Florent Kermarrec
|
dcdf5df4de
|
adapt LiteEth to new SoC
|
2015-04-01 22:50:29 +02:00 |
|
Florent Kermarrec
|
f65c0a3c95
|
adapt LiteScope to new SoC
|
2015-04-01 22:46:24 +02:00 |
|
Florent Kermarrec
|
2d23ab7a85
|
soc/sdram: fix do_finalize
|
2015-04-01 22:38:04 +02:00 |
|
Sebastien Bourdeauducq
|
2900429e65
|
soc: use set
|
2015-04-02 00:14:56 +08:00 |
|
Sebastien Bourdeauducq
|
369086a178
|
soc: simplify integrated memory parameters
|
2015-04-02 00:09:38 +08:00 |
|
Sebastien Bourdeauducq
|
273242b399
|
soc/sdram: minor cleanup
|
2015-04-01 23:41:55 +08:00 |
|
Sebastien Bourdeauducq
|
6e2a662dd7
|
litesata: adapt to new SoC API
|
2015-04-01 17:37:53 +08:00 |
|
Sebastien Bourdeauducq
|
9599eb6fae
|
soc: remove cpu_boot_file argument
|
2015-04-01 17:32:45 +08:00 |
|
Sebastien Bourdeauducq
|
fb86445d14
|
soc: remove cpu_or_bridge and with_cpu arguments
|
2015-04-01 17:29:51 +08:00 |
|
Sebastien Bourdeauducq
|
a148af97ba
|
soc: retrieve csr and memory regions using methods
|
2015-04-01 16:49:32 +08:00 |
|
Sebastien Bourdeauducq
|
8b19a11cd7
|
soc: use add_wb_master function
|
2015-04-01 15:56:54 +08:00 |
|
Sebastien Bourdeauducq
|
2a1112b912
|
soc: simplify/fix csr busword
|
2015-04-01 15:48:56 +08:00 |
|
Sebastien Bourdeauducq
|
04f29e97e2
|
soc: remove unnecessary imports
|
2015-04-01 15:15:09 +08:00 |
|
Sebastien Bourdeauducq
|
5113301130
|
soc: improve memory region conflict check
|
2015-04-01 15:14:02 +08:00 |
|
Sebastien Bourdeauducq
|
980791e2b8
|
soc: remove ns function
|
2015-04-01 14:33:12 +08:00 |
|
Florent Kermarrec
|
b313772a0c
|
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
|
2015-03-29 12:34:40 +02:00 |
|
Florent Kermarrec
|
be20fbabe4
|
soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
|
2015-03-28 23:35:44 +01:00 |
|
Florent Kermarrec
|
0649ded5fd
|
soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
|
2015-03-28 23:10:33 +01:00 |
|
Florent Kermarrec
|
a8d91c0c1d
|
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
|
2015-03-28 16:35:15 +01:00 |
|
Florent Kermarrec
|
75ee8a5db9
|
sdram/phy/simphy: OK with DDR3
|
2015-03-28 01:59:55 +01:00 |
|
Florent Kermarrec
|
51ce7cad6f
|
sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
|
2015-03-28 01:18:35 +01:00 |
|
Florent Kermarrec
|
a95b3f8f13
|
sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
|
2015-03-28 01:17:50 +01:00 |
|
Florent Kermarrec
|
7fe748e1b0
|
sdram/module: clean up tREFI. (use 64ms/8k or 4k)
|
2015-03-28 01:09:21 +01:00 |
|
Florent Kermarrec
|
9137b91e9e
|
sdram: remove nbits from modules and databits from GeomSettings
|
2015-03-26 23:27:37 +01:00 |
|
Florent Kermarrec
|
9a9af17aca
|
sdram/phy/simphy: remove use of iter
|
2015-03-26 23:02:23 +01:00 |
|
Florent Kermarrec
|
e6de4b1bf9
|
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
|
2015-03-26 22:28:32 +01:00 |
|
Florent Kermarrec
|
257706517e
|
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
|
2015-03-26 00:01:42 +01:00 |
|
Florent Kermarrec
|
ff11cb97a9
|
sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
|
2015-03-25 17:22:26 +01:00 |
|
Florent Kermarrec
|
ba8b24df57
|
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
|
2015-03-25 16:57:38 +01:00 |
|
Florent Kermarrec
|
7ea9e2ba89
|
sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
|
2015-03-25 16:56:29 +01:00 |
|
Florent Kermarrec
|
20207c9c32
|
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
|
2015-03-22 11:11:37 +01:00 |
|
Florent Kermarrec
|
c77562f44b
|
liteusb: make oe_n optional on ft2232h phy
|
2015-03-22 10:56:56 +01:00 |
|
Florent Kermarrec
|
ed5746a1fe
|
liteusb: fix imports
|
2015-03-22 10:56:29 +01:00 |
|
Florent Kermarrec
|
92f81409f2
|
sdram/module: fix tREFI on AS4C16M16
|
2015-03-22 03:20:02 +01:00 |
|
Florent Kermarrec
|
30c2521eb0
|
sdram: pass sdram_controller_settings to SDRAMSoC
|
2015-03-21 23:12:18 +01:00 |