28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
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We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
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This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
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This reverts commit ea04947519
2015-03-30 19:41:13 +08:00
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
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This reverts commit 95cfc444e6
2015-03-30 19:41:04 +08:00
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
7fa1cd72a8
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
c0fb0ef600
fhdl/verilog: change the way we initialize reg: reg name = init_value;
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This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
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This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
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This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
2015-03-18 12:08:25 +01:00
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
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it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
e946f6e453
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
2015-03-16 23:47:07 +01:00
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
135a4fea25
fhdl/verilog: fix representation of negative integers
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Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
6f9f08f6eb
add ternary operator sel ? a : b
2013-08-12 13:15:56 +02:00
eb1417c5ed
fhdl: move insert_resets to tools
2013-08-08 11:32:58 +02:00
61b8958953
fix synthesis translate on/off switch
2013-07-26 15:55:16 +02:00
b7ed19c6c5
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
71b89e4c46
fhdl/verilog: lower complex slices before reset insertion
2013-06-30 14:32:47 +02:00
080afdc3f9
fhdl/verilog: fix signedness rules for comparison
2013-06-26 22:45:47 +02:00
b56cb3cefc
fhdl/verilog: improve error reporting
2013-06-24 19:44:25 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
7c4e6c35e5
fhdl/verilog: support special lowering and overrides
2013-02-23 19:03:16 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
3201554f76
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
2013-01-23 15:13:06 +01:00
badba89686
fhdl: support nested statement lists
2013-01-05 14:18:15 +01:00
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
261166d92b
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
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See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
Guy Hutchison
Florent Kermarrec
Sebastien Bourdeauducq
Sebastien Bourdeauducq
Robert Jordens
Nina Engelhardt