Florent Kermarrec
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
Sebastien Bourdeauducq
7c2d0fa641
indentation
2015-06-17 08:32:17 -06:00
Florent Kermarrec
c0bc94ca1c
soc/sdram: add capability to share L2 cache in multi-CPU SoCs
2015-06-17 15:48:45 +02:00
Florent Kermarrec
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
Florent Kermarrec
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
Florent Kermarrec
571ce5791a
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
...
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
Florent Kermarrec
1bb2580779
sdram: use new Migen Converter in Minicon frontend and small cleanup
2015-06-02 19:37:08 +02:00
Florent Kermarrec
f96a856c97
sdram/phy: fix simphy memory usage
2015-06-02 19:33:09 +02:00
Florent Kermarrec
f40140dba5
sdram: refactor minicon and fix issues with DDRx memories
...
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
Sebastien Bourdeauducq
d50bb8c55e
litesata: more doc fixes
2015-05-26 14:13:13 +08:00
Sebastien Bourdeauducq
1e47cfce2b
Merge branch 'master' of https://github.com/m-labs/misoc
...
Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst
2015-05-26 13:57:26 +08:00
Sebastien Bourdeauducq
a9da892b57
litesata: doc fixes
2015-05-26 13:54:31 +08:00
Florent Kermarrec
989d8a7c29
liteata: fix spelling & mistakes in doc
2015-05-26 07:37:09 +02:00
Florent Kermarrec
eb922f6ddc
litesata: rework frontend doc and add striping, mirroring
2015-05-25 14:04:37 +02:00
Florent Kermarrec
0d1a7b9315
litesata: add mirroring
2015-05-25 14:03:14 +02:00
Florent Kermarrec
c3716296ae
litesata/examples_designs: add striping
2015-05-25 14:02:02 +02:00
Florent Kermarrec
0d2db23603
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
2015-05-25 13:55:15 +02:00
Florent Kermarrec
cb053dc011
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
Florent Kermarrec
1bb5a05488
litesata: add striping module for use of multiple HDDs.
2015-05-23 14:12:20 +02:00
Florent Kermarrec
5daba9af68
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
Florent Kermarrec
d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
Florent Kermarrec
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
Florent Kermarrec
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
Florent Kermarrec
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
Florent Kermarrec
4d902b578c
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
2015-05-07 20:03:12 +02:00
Florent Kermarrec
d9111f6a04
litesata: fix packets figure in frontend doc
2015-05-07 11:06:05 +02:00
Florent Kermarrec
5516a49696
litesata: add doc for frontend
2015-05-06 03:57:07 +02:00
Florent Kermarrec
6908ddbaf9
litesata: cleanup README/doc
2015-05-06 02:02:22 +02:00
Florent Kermarrec
7bdcbc94cd
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
...
Works fine @ 3Gbps, still not working @6.0Gbps
2015-05-06 01:33:02 +02:00
Sebastien Bourdeauducq
5d5d5edfe2
spiflash: fix miso bitbang with large DQ
2015-05-06 00:05:25 +08:00
Florent Kermarrec
553262bcc1
soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
2015-05-04 12:28:49 +02:00
Florent Kermarrec
438a0856c5
misoclib/cpu: merge git.py in identifier
2015-05-02 18:42:33 +02:00
Florent Kermarrec
da711ad5f1
liteusb: add simple example design with wishbone bridge and software to control it
2015-05-02 18:21:18 +02:00
Florent Kermarrec
c98bd9fd79
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
2015-05-02 17:07:58 +02:00
Florent Kermarrec
145398d874
liteeth/core/mac: minor cleanup
2015-05-02 16:48:57 +02:00
Florent Kermarrec
e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
Florent Kermarrec
1761bfba8a
litescope/frontend/wishbone: add support for packetized mode
2015-05-02 16:22:43 +02:00
Florent Kermarrec
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
Florent Kermarrec
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
Florent Kermarrec
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
Florent Kermarrec
a4617014f4
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00
Florent Kermarrec
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
Florent Kermarrec
5e649a6577
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
2015-05-01 20:45:04 +02:00
Florent Kermarrec
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
Florent Kermarrec
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
Florent Kermarrec
cd3a51ada6
litescope: fix missing source ack on LiteScopeWishboneBridge
2015-05-01 20:44:57 +02:00
Florent Kermarrec
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec
23126415d3
litescope: use full name in io.py
2015-05-01 17:49:31 +02:00
Florent Kermarrec
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
Florent Kermarrec
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00