27 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	93a615ade4	Merge branch 'new' of github.com:m-labs/misoc into new	2015-10-14 11:11:06 +08:00
Sebastien Bourdeauducq	ecc4c573eb	integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled ... Reported by Florent Kermarrec	2015-10-14 11:09:53 +08:00
Florent Kermarrec	f7787c3c13	software/bios: move romboot after serialboot and netboot ... On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping. Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.	2015-10-13 18:13:00 +02:00
Florent Kermarrec	c38d8175b7	interconnect/stream: add missing part of Demultiplexer	2015-10-05 00:10:55 +02:00
Sebastien Bourdeauducq	9c905830dc	sdram: cleanup	2015-10-02 11:37:22 +08:00
Sebastien Bourdeauducq	d21358fc26	liteeth_mini: fix imports, replace Counter and FlipFlop	2015-09-30 20:17:52 +08:00
Sebastien Bourdeauducq	617c6ecb47	interconnect/stream: add multiplexer and demultiplexer	2015-09-30 19:43:51 +08:00
Sebastien Bourdeauducq	b3d5d1628c	interconnect/stream: remove param, do not depend on FIFO Record support	2015-09-30 16:40:34 +08:00
Sebastien Bourdeauducq	1b8f313d40	lasmicon: do not depend on FIFO Record support	2015-09-30 16:40:04 +08:00
Sebastien Bourdeauducq	c36029fa61	command line options support, CSR CSV, all targets building	2015-09-29 18:14:54 +08:00
Sebastien Bourdeauducq	e1927b7cbb	flterm: cleanup	2015-09-29 18:14:19 +08:00
Sebastien Bourdeauducq	48b6733c33	cores/gpio: fix import	2015-09-29 18:13:59 +08:00
Sebastien Bourdeauducq	dd7dfb0d5e	soc_core: simplify settings (assume CPU and CSR present)	2015-09-29 10:19:42 +08:00
Sebastien Bourdeauducq	b1a90053f5	minor fixes	2015-09-29 10:19:00 +08:00
Sebastien Bourdeauducq	523377efbe	basic out-of-tree build support (OK on PPro)	2015-09-28 20:33:37 +08:00
Sebastien Bourdeauducq	e92d00f767	move software into misoc	2015-09-28 15:30:19 +08:00
Sebastien Bourdeauducq	27b2383607	sdram working on PPro	2015-09-26 21:51:22 +08:00
Sebastien Bourdeauducq	67133f3542	replace flen with len	2015-09-26 18:50:11 +08:00
Sebastien Bourdeauducq	da425d1bcb	add stream, fix CPUs and more imports. simple target boots on ppro.	2015-09-26 16:44:21 +08:00
Sebastien Bourdeauducq	75ef2f9004	fix most imports	2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq	f69674e89c	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
Sebastien Bourdeauducq	ecdc4101b4	lasmicon: enable refresh at all times	2015-09-24 16:01:08 +08:00
Sebastien Bourdeauducq	9b08b037e4	break down sdram, improve consistency of core names	2015-09-24 15:59:55 +08:00
Sebastien Bourdeauducq	0f410e45f1	cores directory	2015-09-24 09:05:10 +08:00
Sebastien Bourdeauducq	83509163df	reorganization WIP: flatten core structure (SDRAM still needs to be done)	2015-09-24 00:18:27 +08:00
Sebastien Bourdeauducq	82236d9b40	migen.fhdl.std -> migen	2015-09-23 00:36:47 +08:00
Sebastien Bourdeauducq	bd74d39338	misoclib -> misoc	2015-09-23 00:35:02 +08:00