78a9579e09
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
2020-05-25 10:46:53 +02:00
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
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Fix UART startbit: 1 cycle later
2020-05-25 10:33:58 +02:00
c75cf45ab4
tools: add litex_jtag_uart to create a virtual uart for the jtag uart.
2020-05-25 10:21:06 +02:00
2cf83b9f69
tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now.
2020-05-25 10:19:16 +02:00
e853ad4b61
fix uart startbit: 1 cycle later
2020-05-24 16:12:07 +02:00
bed5aafd6c
tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...).
...
This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
2020-05-24 10:55:25 +02:00
3833bc3ec3
litex_sim: override uart_name to sim only for serial.
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Using uart_name=crossover is useful to simulate crossover mode.
2020-05-24 09:52:56 +02:00
2fb52e66b1
integration/soc: remove TODO in header.
2020-05-23 18:54:04 +02:00
b65f18c357
cpu/cv32e40p: fix copyright year.
2020-05-23 18:53:03 +02:00
30f3517041
cpu/cv32e40p: add copyright and improve indentation.
2020-05-22 15:55:35 +02:00
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p
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Add support for the CV32E40P RISC-V CPU
2020-05-22 13:44:10 +02:00
9d16b0fc82
libbase: Include missing uart header
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This fixes compilation on mor1kx.
2020-05-22 11:43:18 +02:00
bdc7eb5c48
litex_sim: load SPD data from files in hexdump format as printed in BIOS
2020-05-21 16:20:06 +02:00
a42dc97401
bios/sdram: add BIOS command for reading SPD
2020-05-21 14:32:31 +02:00
8fd3e74ec9
bios/sdram: add firmware for reading SPD EEPROM
2020-05-21 14:07:42 +02:00
42350f6d83
platforms/targets: keep in sync with litex-boards.
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- LedChaser.
- use of soc.build_name in load/flash bitstream.
2020-05-21 09:14:33 +02:00
2eea786436
build/sim: rename dut to sim (for consistency with other builds).
2020-05-21 09:06:29 +02:00
a6cbbc9d69
integration/soc: set build_name to platform.name when not specified.
2020-05-21 09:05:45 +02:00
16417cb8f1
software/liblitespi: fix #endif location.
2020-05-20 23:20:45 +02:00
9bdb063b3e
Merge pull request #516 from antmicro/i2s_support_arty
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Add I2S support to Arty
2020-05-20 19:49:42 +02:00
7c5f56c207
litex/sim: fix compiler warnings
2020-05-20 15:34:19 +02:00
ce49990084
Extend I2S capabilities
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This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
2d6ee5aaf2
cores/cpu: add cv32e40p
2020-05-20 13:46:37 +02:00
ca8cb83424
software/bios/isr: add support for cv32e40p
2020-05-20 13:46:37 +02:00
ab41e27e4c
software/liblitespi/spiflash: fix dummy bits setup function name
2020-05-20 11:47:40 +02:00
bd0f21ba85
targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets).
...
The LiteSPI integration can be prototype in the LiteSPI example designs. Once mature and
fully tested, we could integrate it to the targets.
2020-05-20 11:18:59 +02:00
80eca3000b
software/liblitespi/spiflash: review/simplify/update and test on arty.
2020-05-20 11:16:39 +02:00
4a1756208d
build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling.
2020-05-20 10:00:39 +02:00
e91c317139
software/bios: cleanup includes and specify the lib in the include.
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This ease understanding from which lib the file is included and also allow
having simple filenames in the libs.
2020-05-20 09:55:19 +02:00
c3a03d0d99
software: create liblitespi and mode litespi code to it (with some parts commented out for now).
2020-05-20 09:32:45 +02:00
61238beeae
soc/software/bios: add autoconfiguration functionality for LiteSPI core
2020-05-20 09:16:07 +02:00
c5524dbf20
software/bios: fix link order to avoid undefined symbol errors
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-19 16:20:58 -04:00
b4267a7901
build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set.
2020-05-19 16:21:52 +02:00
de7e0ee9ff
integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed.
2020-05-19 16:01:57 +02:00
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
109fd2674a
integration/builder: simplify default output_dir to "build/platform".
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All SoC are now based on the same base class and naming was too complicated.
2020-05-19 13:59:56 +02:00
7192397ab4
software/libbase: remove linker-sdram (unused).
2020-05-18 23:35:48 +02:00
b4b84def3c
software/bios: mode spisdcard code to liblitesdcard.
2020-05-18 23:33:34 +02:00
21e2a34c3f
software/bios: rename commands to cmds and update with libs' names.
2020-05-18 23:26:51 +02:00
33f6ce7431
software/bios: move hw flags definitions to respective libs, remove hw/flags.h.
2020-05-18 23:09:31 +02:00
403355a8ed
software: create liblitescard and move sdcard init/test code to it.
2020-05-18 22:49:12 +02:00
920d0ee536
software: create liblitedram and move sdram init/test code to it.
2020-05-18 22:42:23 +02:00
c95084e5c6
bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash.
2020-05-18 22:24:24 +02:00
573a881529
software/bios/commands: rename cmd_mdio to cmd_liteeth.
2020-05-18 22:16:20 +02:00
ff8d9e61bf
software/bios: move mdio to libliteeth.
2020-05-18 21:09:41 +02:00
70a67ce7ed
software/bios: rename libnet to libliteeth and move all ethernet files to it.
2020-05-18 21:04:54 +02:00
56b8723b72
software/bios: rename cmd_mem_access to cmd_mem.
2020-05-18 19:59:28 +02:00
a02077d547
cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.
2020-05-18 17:30:42 +02:00
b5352f403c
cpu/microwatt: update microwatt_wraper.vhdl
2020-05-18 16:38:08 +02:00
be25500e91
uptime: rework and integrate it in Timer to ease software support.
2020-05-17 11:05:14 +02:00
d6549ff8f1
bios: add uptime command and rewrite cmd_bios comments.
2020-05-16 10:02:31 +02:00
fc0e55be32
soc: improve uptime comments.
2020-05-16 10:01:39 +02:00
840679add6
Merge pull request #526 from rprinz08/master
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Make booting from SD-Card to behave same as from SPI flash
2020-05-15 16:03:37 +02:00
82364de57f
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
2020-05-15 15:00:04 +02:00
3f649077b1
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 12:07:52 +02:00
3391398a5f
bios/sdram: always show bitslip on two digits to keep scan aligned.
2020-05-14 15:20:52 +02:00
1e35b0e705
csr: Rework accessors
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Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 21:38:19 +10:00
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base
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export: add define of CSR_BASE if not already defined and use it for …
2020-05-14 08:02:37 +02:00
9d9e7d54cd
Update litex_term help
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Specify the use of kernel address with flash flag.
2020-05-13 22:50:09 +02:00
2e59dc329d
platforms/nexys4ddr: add card detect pin to sdcard.
2020-05-13 19:11:46 +02:00
51742be2bb
integration/soc: review/simplify interconnect and add logger.info.
2020-05-13 18:29:12 +02:00
1ed6869110
soc: Revive generation of a PointToPoint interconnect
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When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
748ef1add3
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
...
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
9d1443c1a8
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
2020-05-13 09:31:20 +02:00
5ea3bae036
bios/boot: review/fix #503 .
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- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
bf7857f553
Merge pull request #503 from rprinz08/master
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BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
d2d82dacf2
Bios linker edits to prevent inappropriate optimisation
2020-05-12 23:32:49 +01:00
1f55fcf449
fixed bug in BIOS spi flash "fw" command
2020-05-12 16:58:42 +02:00
f062c0c44b
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
2020-05-12 16:57:21 +02:00
3fb99b7d33
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
2020-05-12 16:51:47 +02:00
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
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Extended SPI flash support
2020-05-12 16:42:01 +02:00
7d79da8eda
Merge pull request #510 from mubes/colorlight_usb
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Colorlight usb
2020-05-12 16:35:29 +02:00
3a6dd95d6f
integration/soc: review/simplify changes for standalone cores.
...
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
8499733289
Fix dumb missing line
2020-05-12 14:40:11 +01:00
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
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Improve standalone cores
2020-05-12 14:55:44 +02:00
873d95e517
interconnect/wishbonebridge: refresh/simplify.
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This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
2020-05-12 13:40:28 +02:00
f628ff6b47
WB2CSR: Use CSR address_width for the wishbone bus
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Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
520c17e96d
soc_core: Add option to override CSR base
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When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
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The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
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When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
33e202edd4
Bring into line with master
2020-05-12 12:28:09 +01:00
dcc881db92
soc: Don't create a share intercon with only one master and one slave
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This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
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Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
dc1d452008
Addition of boot address parameter for trellis builds
2020-05-12 09:41:37 +01:00
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
5e4a436089
Vivado Command Update for Systemverilog
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Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
3ce9010083
Merge pull request #505 from DurandA/patch-3
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Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
1e610600f6
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
2020-05-11 10:52:39 +02:00
ebcf67c10f
Merge pull request #502 from shuffle2/master
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diamond: project generation improvements
2020-05-11 09:55:52 +02:00
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
c9e36d7fdd
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
2020-05-11 09:33:26 +02:00
ea7fe383a3
lattice/trellis: simplify seed support and add it to trellis_args.
2020-05-11 09:26:12 +02:00
5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
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Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
2d70220b80
bios: Fix warning on 64-bit
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This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
Florent Kermarrec
David Jablonski
Mateusz Hołenko
Jędrzej Boczar
Franck Jullien
Pawel Sagan
Piotr Binkowski
Jan Kowalewski
Gabriel Somlo
rprinz08
Benjamin Herrenschmidt
Arnaud Durand
Dave Marples
Kamil Rakoczy
sadullah
Ilia Sergachev