ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
eeee179dd8
diamond: close project when done
...
Avoids ".recovery file is present" prompt.
2020-05-09 02:28:00 -07:00
9b782bd7da
diamond: clock constraint improvements
...
Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
2020-05-09 02:28:00 -07:00
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
162d32603d
Merge pull request #500 from mubes/fixups
...
Fixups
2020-05-07 11:55:58 +02:00
d74f8fc93d
build/xilinx: add disable_constraints parameter to Platform.add_ip.
...
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
2020-05-07 11:34:26 +02:00
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
8b9aa16d2e
boards/platforms: update xilinx programmers.
2020-05-06 16:16:41 +02:00
3c34039b73
build/xilinx/vivado: ensure Vivado process our .xdc early.
...
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
2020-05-06 13:13:01 +02:00
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
...
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
0aa3c339cc
targets/genesys2: set cmd_latency to 1.
2020-05-05 16:33:14 +02:00
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
22bcbec03a
boards: keep in sync with LiteX-Boards, integrate improvements.
...
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
2020-05-05 15:27:56 +02:00
28f85c7403
build/lattice/programmer: add UJProg (for ULX3S).
2020-05-05 13:31:58 +02:00
85ac5ef133
build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer.
2020-05-05 12:17:12 +02:00
9a7f9cb87b
build/generic_programmer: catch 404 not found when downloading config/proxy.
2020-05-05 12:16:29 +02:00
d0b8daa005
build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request.
...
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")
This allows some try/except simplifications on constraints.
2020-05-05 11:23:46 +02:00
b8f9f83a8f
build/openocd: add find_config method to allow using local config file or download it if not available locally.
2020-05-05 09:56:13 +02:00
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output
...
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
2020-05-01 21:18:09 +02:00
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
83f4dcb2c6
Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
ac1e968351
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-04-28 22:25:57 +02:00
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
f71014b9fb
diamond: fix include paths
...
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
...
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
65e6ddc6cd
lattice/common: add LatticeECP5DDRInput.
2020-04-22 10:13:28 +02:00
2031f28057
lattice/common: cleanup instances, simplify tritates.
2020-04-22 09:07:38 +02:00
2d25bcb09c
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
2020-04-22 09:07:33 +02:00
56e1528455
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:38:24 +02:00
08e4dc02ec
tools/remote/etherbone: update import.
2020-04-17 21:30:33 +02:00
b0f8ee9876
litex_sim: add option to create SDRAM module from SPD data
2020-04-17 14:52:53 +02:00
19f983c420
targets: manual define of the SDRAM PHY no longer needed.
2020-04-16 11:26:59 +02:00
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
3915ed9760
litex_sim: add phytype to PhySettings.
2020-04-16 10:22:43 +02:00
c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
...
Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
...
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
f4b345ecd7
build/lattice/trellis.py: Add 12k device
...
nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
c96d1e6672
Fix import for data.
2020-04-11 18:37:06 -07:00
69367f8d4e
Make litex a namespace.
2020-04-11 18:37:06 -07:00
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
5a0bb6ee01
litex_sim: Rework Makefiles to put output files in gateware directory.
2020-04-11 18:37:03 -07:00
a0658421cc
litex_sim: Better error messages on failure to load module.
2020-04-11 18:35:39 -07:00
b95e0a19b1
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
2020-04-10 15:50:35 +02:00
40f43efcf6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:41:01 +02:00
292d6b75b6
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
2020-04-10 14:38:22 +02:00
88dc5158c1
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
2020-04-10 14:37:29 +02:00
fdadbd868b
build/lattice/common: remove multi-bits support on SDRInput/Output.
2020-04-10 14:36:13 +02:00
8159b65bee
litex/build/io: also import CRG (since using DifferentialInput).
2020-04-10 10:25:21 +02:00
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
...
This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
2e270cf28c
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
2020-04-09 23:08:59 +02:00
deebc49ab0
boards/platforms: cosmetic cleanups.
2020-04-09 23:04:29 +02:00
3c0ba8ae62
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
2020-04-09 18:55:01 +02:00
6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
...
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
...
Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
a67ab41835
interconnect/csr: add reset_less parameter.
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In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
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Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
a35df4f7d1
stream: set reset_less to True on datapath signals.
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Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
27f00851d0
Merge pull request #447 from antmicro/spi-xip
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Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
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This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
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Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
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In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
c6b6dee2e7
software/bios: factor out busy_wait() function
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
540218b2d8
software/libbase/spisdcard: fix width of address parameter
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Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
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The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
5a402264d0
Fix off-by-one error on almost full condition for prefetch
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This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
rprinz08
Shawn Hoffman
Florent Kermarrec
Dave Marples
Benjamin Herrenschmidt
Gabriel Somlo
Sadullah Canakci
Franck Jullien
David Shah
Ilya Epifanov
bunnie
Jakub Cebulski
Greg Davill
Jędrzej Boczar
Mateusz Holenko
Tim 'mithro' Ansell
Rangel Ivanov
David Sawatzke
kessam
Piotr Binkowski
Feliks