d6549ff8f1
bios: add uptime command and rewrite cmd_bios comments.
2020-05-16 10:02:31 +02:00
fc0e55be32
soc: improve uptime comments.
2020-05-16 10:01:39 +02:00
840679add6
Merge pull request #526 from rprinz08/master
...
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 16:03:37 +02:00
82364de57f
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
2020-05-15 15:00:04 +02:00
3f649077b1
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 12:07:52 +02:00
3391398a5f
bios/sdram: always show bitslip on two digits to keep scan aligned.
2020-05-14 15:20:52 +02:00
1e35b0e705
csr: Rework accessors
...
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 21:38:19 +10:00
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base
...
export: add define of CSR_BASE if not already defined and use it for …
2020-05-14 08:02:37 +02:00
9d9e7d54cd
Update litex_term help
...
Specify the use of kernel address with flash flag.
2020-05-13 22:50:09 +02:00
2e59dc329d
platforms/nexys4ddr: add card detect pin to sdcard.
2020-05-13 19:11:46 +02:00
51742be2bb
integration/soc: review/simplify interconnect and add logger.info.
2020-05-13 18:29:12 +02:00
1ed6869110
soc: Revive generation of a PointToPoint interconnect
...
When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
748ef1add3
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
...
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
9d1443c1a8
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
2020-05-13 09:31:20 +02:00
5ea3bae036
bios/boot: review/fix #503 .
...
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
bf7857f553
Merge pull request #503 from rprinz08/master
...
BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
d2d82dacf2
Bios linker edits to prevent inappropriate optimisation
2020-05-12 23:32:49 +01:00
1f55fcf449
fixed bug in BIOS spi flash "fw" command
2020-05-12 16:58:42 +02:00
f062c0c44b
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
2020-05-12 16:57:21 +02:00
3fb99b7d33
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
2020-05-12 16:51:47 +02:00
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
...
Extended SPI flash support
2020-05-12 16:42:01 +02:00
7d79da8eda
Merge pull request #510 from mubes/colorlight_usb
...
Colorlight usb
2020-05-12 16:35:29 +02:00
3a6dd95d6f
integration/soc: review/simplify changes for standalone cores.
...
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
8499733289
Fix dumb missing line
2020-05-12 14:40:11 +01:00
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
...
Improve standalone cores
2020-05-12 14:55:44 +02:00
873d95e517
interconnect/wishbonebridge: refresh/simplify.
...
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
2020-05-12 13:40:28 +02:00
f628ff6b47
WB2CSR: Use CSR address_width for the wishbone bus
...
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
520c17e96d
soc_core: Add option to override CSR base
...
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
...
The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
...
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
33e202edd4
Bring into line with master
2020-05-12 12:28:09 +01:00
dcc881db92
soc: Don't create a share intercon with only one master and one slave
...
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
...
Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
dc1d452008
Addition of boot address parameter for trellis builds
2020-05-12 09:41:37 +01:00
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
5e4a436089
Vivado Command Update for Systemverilog
...
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
3ce9010083
Merge pull request #505 from DurandA/patch-3
...
Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
1e610600f6
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
2020-05-11 10:52:39 +02:00
ebcf67c10f
Merge pull request #502 from shuffle2/master
...
diamond: project generation improvements
2020-05-11 09:55:52 +02:00
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
c9e36d7fdd
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
2020-05-11 09:33:26 +02:00
ea7fe383a3
lattice/trellis: simplify seed support and add it to trellis_args.
2020-05-11 09:26:12 +02:00
5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
...
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
2d70220b80
bios: Fix warning on 64-bit
...
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
eeee179dd8
diamond: close project when done
...
Avoids ".recovery file is present" prompt.
2020-05-09 02:28:00 -07:00
9b782bd7da
diamond: clock constraint improvements
...
Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
2020-05-09 02:28:00 -07:00
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
162d32603d
Merge pull request #500 from mubes/fixups
...
Fixups
2020-05-07 11:55:58 +02:00
d74f8fc93d
build/xilinx: add disable_constraints parameter to Platform.add_ip.
...
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
2020-05-07 11:34:26 +02:00
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
8b9aa16d2e
boards/platforms: update xilinx programmers.
2020-05-06 16:16:41 +02:00
3c34039b73
build/xilinx/vivado: ensure Vivado process our .xdc early.
...
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
2020-05-06 13:13:01 +02:00
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
...
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
0aa3c339cc
targets/genesys2: set cmd_latency to 1.
2020-05-05 16:33:14 +02:00
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
22bcbec03a
boards: keep in sync with LiteX-Boards, integrate improvements.
...
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
2020-05-05 15:27:56 +02:00
28f85c7403
build/lattice/programmer: add UJProg (for ULX3S).
2020-05-05 13:31:58 +02:00
85ac5ef133
build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer.
2020-05-05 12:17:12 +02:00
9a7f9cb87b
build/generic_programmer: catch 404 not found when downloading config/proxy.
2020-05-05 12:16:29 +02:00
d0b8daa005
build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request.
...
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")
This allows some try/except simplifications on constraints.
2020-05-05 11:23:46 +02:00
b8f9f83a8f
build/openocd: add find_config method to allow using local config file or download it if not available locally.
2020-05-05 09:56:13 +02:00
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output
...
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
2020-05-01 21:18:09 +02:00
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
83f4dcb2c6
Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
ac1e968351
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-04-28 22:25:57 +02:00
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
f71014b9fb
diamond: fix include paths
...
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
...
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
Florent Kermarrec
rprinz08
Benjamin Herrenschmidt
Arnaud Durand
Dave Marples
Kamil Rakoczy
sadullah
Ilia Sergachev
Shawn Hoffman
Gabriel Somlo
Franck Jullien
David Shah
Ilya Epifanov
bunnie
Jakub Cebulski
Greg Davill
Jędrzej Boczar