3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
83f4dcb2c6
Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
ac1e968351
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-04-28 22:25:57 +02:00
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
f71014b9fb
diamond: fix include paths
...
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
...
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
65e6ddc6cd
lattice/common: add LatticeECP5DDRInput.
2020-04-22 10:13:28 +02:00
2031f28057
lattice/common: cleanup instances, simplify tritates.
2020-04-22 09:07:38 +02:00
2d25bcb09c
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
2020-04-22 09:07:33 +02:00
56e1528455
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:38:24 +02:00
08e4dc02ec
tools/remote/etherbone: update import.
2020-04-17 21:30:33 +02:00
b0f8ee9876
litex_sim: add option to create SDRAM module from SPD data
2020-04-17 14:52:53 +02:00
19f983c420
targets: manual define of the SDRAM PHY no longer needed.
2020-04-16 11:26:59 +02:00
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
3915ed9760
litex_sim: add phytype to PhySettings.
2020-04-16 10:22:43 +02:00
c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
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Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
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Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
...
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
f4b345ecd7
build/lattice/trellis.py: Add 12k device
...
nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
c96d1e6672
Fix import for data.
2020-04-11 18:37:06 -07:00
69367f8d4e
Make litex a namespace.
2020-04-11 18:37:06 -07:00
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
5a0bb6ee01
litex_sim: Rework Makefiles to put output files in gateware directory.
2020-04-11 18:37:03 -07:00
a0658421cc
litex_sim: Better error messages on failure to load module.
2020-04-11 18:35:39 -07:00
b95e0a19b1
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
2020-04-10 15:50:35 +02:00
40f43efcf6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:41:01 +02:00
292d6b75b6
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
2020-04-10 14:38:22 +02:00
88dc5158c1
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
2020-04-10 14:37:29 +02:00
fdadbd868b
build/lattice/common: remove multi-bits support on SDRInput/Output.
2020-04-10 14:36:13 +02:00
8159b65bee
litex/build/io: also import CRG (since using DifferentialInput).
2020-04-10 10:25:21 +02:00
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
...
This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
2e270cf28c
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
2020-04-09 23:08:59 +02:00
deebc49ab0
boards/platforms: cosmetic cleanups.
2020-04-09 23:04:29 +02:00
3c0ba8ae62
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
2020-04-09 18:55:01 +02:00
6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
...
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
...
Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
27f00851d0
Merge pull request #447 from antmicro/spi-xip
...
Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
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Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
...
In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
c6b6dee2e7
software/bios: factor out busy_wait() function
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
540218b2d8
software/libbase/spisdcard: fix width of address parameter
...
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
...
The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
5a402264d0
Fix off-by-one error on almost full condition for prefetch
...
This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
c547b2cc29
Merge pull request #436 from rob-ng15/master
...
Reclock spi sdcard access after initialisation
2020-03-21 09:26:25 +01:00
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider
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soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
2020-03-21 09:25:37 +01:00
2bf31a31da
Reclock spi sdcard access after initialisation
...
Depends upon https://github.com/enjoy-digital/litex/pull/435
After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.
Tested with the card being clocked to 12.5MHz on de10nano
2020-03-21 07:37:21 +00:00
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
4e9a8ffe9c
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-20 22:02:36 +01:00
61c9e54a90
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
2020-03-20 19:49:42 +01:00
dd7718b4fe
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:58:31 +01:00
fca52d110d
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-20 18:54:51 +01:00
f3c233776e
Use <stdint.h> to provide structure sizes
2020-03-20 11:35:05 +00:00
c2ebbcbf6c
Use <stdint.h> for structure sizes
2020-03-20 11:34:24 +00:00
ccf7363932
integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
2020-03-20 10:24:31 +01:00
ec3e068669
targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.
2020-03-20 09:58:09 +01:00
d276036f24
integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC.
2020-03-20 09:57:37 +01:00
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard
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Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
2020-03-20 09:41:56 +01:00
b960d7c574
targets/nexys4ddr: add '--with-spi-sdcard' build option
2020-03-19 21:51:44 -04:00
7a7b8905b7
platforms/nexys4ddr: add spisdcard pins.
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Synchronize with litex-boards commit #57bcadb.
2020-03-19 21:51:44 -04:00
af4de03fad
targets/nexys4ddr: make sdcard reset conditional
2020-03-19 21:51:44 -04:00
a33916bc6b
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
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On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 21:51:44 -04:00
279886721b
Don't let python convert lane number to float.
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While at it also:
* Don't multilane for reg >= 8 bit width.
* Only check if we should switch to multilane after finding min field width.
2020-03-19 18:12:41 -07:00
1f90abea8e
bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv
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When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 19:37:47 -04:00
c2938dc973
bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency
2020-03-19 19:37:47 -04:00
dd07a0ad2f
Merge pull request #431 from antmicro/hybrid-mac
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litex_sim: add support for hybrid mac
2020-03-19 22:10:33 +01:00
37f25ed37a
software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions.
2020-03-19 11:02:15 +01:00
939256340f
software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR).
2020-03-19 10:47:28 +01:00
8fe9e72f7b
Merge pull request #429 from rob-ng15/master
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SPI hardware bitbanging from SD CARD
2020-03-19 10:41:09 +01:00
96a265a408
litex_sim: add support for hybrid mac
2020-03-19 10:04:08 +01:00
b2103f4ad8
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
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Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-18 15:11:23 -04:00
e865162904
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:05:54 +01:00
27720409ce
SPI hardware bitbanging from SD CARD
2020-03-17 09:51:11 +00:00
d45dda731a
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:45 +00:00
50b6db6a6b
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:16 +00:00
2c4b89639f
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
2020-03-16 11:44:39 +01:00
57576fa8fc
Add bit more logic to decide when to switch to multilane CSR documentation.
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Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
2020-03-13 14:48:56 -07:00
dda7a8c5f3
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
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In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
2020-03-13 14:48:23 -07:00
aec1bfbeb4
cores/clock: simplify Fractional Divide support on S7MMCM.
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Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
2020-03-13 15:56:39 +01:00
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
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add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
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Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
c304c4db27
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
2020-03-13 09:37:42 +01:00
d063acb767
Updating the vendored wavedrom js files.
2020-03-12 22:35:04 -07:00
a27385a79c
soc/intergration: rename mr_memory_x parameter to memory_x.
2020-03-12 12:20:48 +01:00
4d02263223
Add --mr-memory-x parameter to generate memory regions memory.x file.
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This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
e9f0ff68ce
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-11 12:57:29 +01:00
979f98ea31
software: revert LTO changes (Disable it).
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It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417 ).
2020-03-11 12:57:00 +01:00
01b6969375
Merge pull request #422 from xobs/core-doc-fixes
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Core doc fixes
2020-03-11 19:38:42 +08:00
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
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integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
bb8905fa5d
cores/gpio: add CSR descriptions.
2020-03-11 12:06:15 +01:00
4dabc5a625
cores/icap: add CSR descriptions.
2020-03-11 11:04:42 +01:00
77132a48b0
cores/spi: add CSR descriptions.
2020-03-11 10:58:32 +01:00
6d861c6e57
cores/pwm: add CSR descriptions.
2020-03-11 10:38:28 +01:00
cbc1f5949d
cores/xadc: add CSR descriptions.
2020-03-11 10:05:14 +01:00
a904034811
integration/soc: add_ethernet: honor self.map["ethmac"], if present
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
846a2720b7
targets/kcu105: move cd_pll4x.
2020-03-10 17:02:28 +01:00
c97fabb285
targets/kcu105: simplify CRG using USIDELAYCTRL.
2020-03-10 16:48:07 +01:00
3c0b97eec8
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
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This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
a2f61b4e80
soc/cores/spi_opi: documentation fixes
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The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
d2f6139dc7
soc/cores/i2s: fix rst parsing errors
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The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
bcbf558b6b
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
2020-03-10 13:08:49 +01:00
5b92bf2d57
add fractional division options to clk0 config on PLL
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S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
2020-03-10 18:48:30 +08:00
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
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software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
b509068790
cores/clock: add logging to visualize clkin/clkouts and computed config.
2020-03-10 11:13:16 +01:00
04b8a91255
integration/soc: add FPGA device and System clock to logs.
2020-03-10 11:10:23 +01:00
02cba41d64
targets/icebreaker: create CRG after SoC.
2020-03-10 11:09:56 +01:00
4d15e1f7f8
software/bios: fixup for Ultrascale SDRAM debug
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Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
ba2f31d43d
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
2020-03-09 19:36:47 +01:00
8808c884c5
boards/platforms/icebreaker: cleanup a bit.
2020-03-09 19:16:02 +01:00
4656b1b2ad
software/common: fix LTO checks.
2020-03-09 19:08:27 +01:00
2a91deadcb
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-03-09 19:03:05 +01:00
38d7f8a6e6
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
2020-03-09 19:02:23 +01:00
1e9aa64387
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
2020-03-09 19:01:16 +01:00
197bdcb026
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
2020-03-09 16:51:18 +01:00
37869e38b8
boards: add initial icebreaker platform/target from litex-boards.
2020-03-09 11:56:55 +01:00
72af1b39eb
software/bios: add Ultrascale SDRAM debug functions.
2020-03-09 10:55:31 +01:00
6480d1803e
boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:37:31 +01:00
b02c23391a
integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2.
2020-03-08 19:17:31 +01:00
e801dc0261
soc: allow creating SoC without BIOS.
...
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
2020-03-06 20:05:27 +01:00
ecca3d801d
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
2020-03-06 14:53:59 +01:00
69ffafd81d
integration/builder: generate csr maps before compiling software.
2020-03-06 14:20:32 +01:00
e2dab06386
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
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This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
2020-03-06 14:12:58 +01:00
e124aed9a2
software/common.mak: fix LTO refactoring issue.
2020-03-05 23:42:36 +01:00
da580e31fd
Fix copyrights
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:44:10 +01:00
020bef4197
targets/nexys4ddr: fix sdcard clocker initialization
2020-03-05 09:02:29 -05:00
9249fc90cf
Merge pull request #410 from antmicro/netv2-edid
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platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:43:02 +01:00
72f63243cd
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:27:47 +01:00
ad11ff39ad
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 11:19:29 +01:00
3770195048
bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes.
2020-03-04 18:33:08 +01:00
4c83c975b1
doc: align to improve readability.
2020-03-04 16:46:56 +01:00
4f935714de
soc/doc: remove soc.get_csr_regions support.
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Now that SoC documentation is integrated in LiteX, this is no longer needed.
2020-03-04 16:27:11 +01:00
6893222cf1
bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help.
2020-03-04 15:53:18 +01:00
0b923aa497
build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.
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Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.
This also removes distutils dependency.
2020-03-04 09:13:26 +01:00
1d7c6943af
software/common: add LTO enable flag and cleanup.
2020-03-04 08:11:21 +01:00
b29f443fe5
litex_sim: fix with_uart parameter.
2020-03-03 19:04:18 +01:00
98e41e2e0d
targets/nexys4ddr: add default kwargs parameters.
2020-03-02 09:44:20 +01:00
598ad692a0
Merge branch 'master' of https://github.com/enjoy-digital/litex
2020-03-02 09:31:45 +01:00
a67e19c660
integration/soc_core: change disable parameters to no-xxyy.
2020-03-02 09:31:32 +01:00
ddb264f3fd
Merge pull request #405 from sajattack/sifive-triple
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add riscv-sifive-elf triple
2020-03-02 09:30:05 +01:00
156a85b15b
integration/soc: add auto_int type and use it on all int parameters.
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Allow passing parameters as int or hex values.
2020-03-02 09:08:30 +01:00
7e96c911b9
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
2020-03-02 09:01:05 +01:00
cb0371b330
integration/soc: add ethphy CSR in target.
2020-03-02 08:42:59 +01:00
f27225c2de
targets/nexys4ddr: use soc.add_ethernet method.
2020-03-01 21:21:01 +01:00
9735bd5bf2
integration/soc: add add_ethernet method.
2020-03-01 20:50:13 +01:00
Florent Kermarrec
Franck Jullien
David Shah
Ilya Epifanov
bunnie
Jakub Cebulski
shuffle2
Greg Davill
Jędrzej Boczar
Mateusz Holenko
Tim 'mithro' Ansell
Rangel Ivanov
David Sawatzke
kessam
Piotr Binkowski
Gabriel Somlo
Feliks
rob-ng15
Piotr Esden-Tempski
Sean Cross
Karol Gugala