970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
27f00851d0
Merge pull request #447 from antmicro/spi-xip
...
Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
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Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
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In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
c6b6dee2e7
software/bios: factor out busy_wait() function
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
540218b2d8
software/libbase/spisdcard: fix width of address parameter
...
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
...
The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
5a402264d0
Fix off-by-one error on almost full condition for prefetch
...
This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
c547b2cc29
Merge pull request #436 from rob-ng15/master
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Reclock spi sdcard access after initialisation
2020-03-21 09:26:25 +01:00
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider
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soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
2020-03-21 09:25:37 +01:00
2bf31a31da
Reclock spi sdcard access after initialisation
...
Depends upon https://github.com/enjoy-digital/litex/pull/435
After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.
Tested with the card being clocked to 12.5MHz on de10nano
2020-03-21 07:37:21 +00:00
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
4e9a8ffe9c
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-20 22:02:36 +01:00
61c9e54a90
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
2020-03-20 19:49:42 +01:00
dd7718b4fe
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:58:31 +01:00
fca52d110d
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-20 18:54:51 +01:00
f3c233776e
Use <stdint.h> to provide structure sizes
2020-03-20 11:35:05 +00:00
c2ebbcbf6c
Use <stdint.h> for structure sizes
2020-03-20 11:34:24 +00:00
ccf7363932
integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
2020-03-20 10:24:31 +01:00
ec3e068669
targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.
2020-03-20 09:58:09 +01:00
d276036f24
integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC.
2020-03-20 09:57:37 +01:00
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard
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Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
2020-03-20 09:41:56 +01:00
b960d7c574
targets/nexys4ddr: add '--with-spi-sdcard' build option
2020-03-19 21:51:44 -04:00
7a7b8905b7
platforms/nexys4ddr: add spisdcard pins.
...
Synchronize with litex-boards commit #57bcadb.
2020-03-19 21:51:44 -04:00
af4de03fad
targets/nexys4ddr: make sdcard reset conditional
2020-03-19 21:51:44 -04:00
a33916bc6b
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
...
On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 21:51:44 -04:00
279886721b
Don't let python convert lane number to float.
...
While at it also:
* Don't multilane for reg >= 8 bit width.
* Only check if we should switch to multilane after finding min field width.
2020-03-19 18:12:41 -07:00
1f90abea8e
bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv
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When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 19:37:47 -04:00
c2938dc973
bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency
2020-03-19 19:37:47 -04:00
dd07a0ad2f
Merge pull request #431 from antmicro/hybrid-mac
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litex_sim: add support for hybrid mac
2020-03-19 22:10:33 +01:00
37f25ed37a
software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions.
2020-03-19 11:02:15 +01:00
939256340f
software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR).
2020-03-19 10:47:28 +01:00
8fe9e72f7b
Merge pull request #429 from rob-ng15/master
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SPI hardware bitbanging from SD CARD
2020-03-19 10:41:09 +01:00
96a265a408
litex_sim: add support for hybrid mac
2020-03-19 10:04:08 +01:00
b2103f4ad8
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
...
Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-18 15:11:23 -04:00
e865162904
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:05:54 +01:00
27720409ce
SPI hardware bitbanging from SD CARD
2020-03-17 09:51:11 +00:00
d45dda731a
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:45 +00:00
50b6db6a6b
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:16 +00:00
2c4b89639f
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
2020-03-16 11:44:39 +01:00
57576fa8fc
Add bit more logic to decide when to switch to multilane CSR documentation.
...
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
2020-03-13 14:48:56 -07:00
dda7a8c5f3
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
...
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
2020-03-13 14:48:23 -07:00
aec1bfbeb4
cores/clock: simplify Fractional Divide support on S7MMCM.
...
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
2020-03-13 15:56:39 +01:00
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
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add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
...
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
c304c4db27
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
2020-03-13 09:37:42 +01:00
d063acb767
Updating the vendored wavedrom js files.
2020-03-12 22:35:04 -07:00
a27385a79c
soc/intergration: rename mr_memory_x parameter to memory_x.
2020-03-12 12:20:48 +01:00
4d02263223
Add --mr-memory-x parameter to generate memory regions memory.x file.
...
This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
e9f0ff68ce
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-11 12:57:29 +01:00
979f98ea31
software: revert LTO changes (Disable it).
...
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417 ).
2020-03-11 12:57:00 +01:00
01b6969375
Merge pull request #422 from xobs/core-doc-fixes
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Core doc fixes
2020-03-11 19:38:42 +08:00
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
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integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
bb8905fa5d
cores/gpio: add CSR descriptions.
2020-03-11 12:06:15 +01:00
4dabc5a625
cores/icap: add CSR descriptions.
2020-03-11 11:04:42 +01:00
77132a48b0
cores/spi: add CSR descriptions.
2020-03-11 10:58:32 +01:00
6d861c6e57
cores/pwm: add CSR descriptions.
2020-03-11 10:38:28 +01:00
cbc1f5949d
cores/xadc: add CSR descriptions.
2020-03-11 10:05:14 +01:00
a904034811
integration/soc: add_ethernet: honor self.map["ethmac"], if present
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
846a2720b7
targets/kcu105: move cd_pll4x.
2020-03-10 17:02:28 +01:00
c97fabb285
targets/kcu105: simplify CRG using USIDELAYCTRL.
2020-03-10 16:48:07 +01:00
3c0b97eec8
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
...
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
a2f61b4e80
soc/cores/spi_opi: documentation fixes
...
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
d2f6139dc7
soc/cores/i2s: fix rst parsing errors
...
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
bcbf558b6b
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
2020-03-10 13:08:49 +01:00
5b92bf2d57
add fractional division options to clk0 config on PLL
...
S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
2020-03-10 18:48:30 +08:00
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
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software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
b509068790
cores/clock: add logging to visualize clkin/clkouts and computed config.
2020-03-10 11:13:16 +01:00
04b8a91255
integration/soc: add FPGA device and System clock to logs.
2020-03-10 11:10:23 +01:00
02cba41d64
targets/icebreaker: create CRG after SoC.
2020-03-10 11:09:56 +01:00
4d15e1f7f8
software/bios: fixup for Ultrascale SDRAM debug
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Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
ba2f31d43d
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
2020-03-09 19:36:47 +01:00
8808c884c5
boards/platforms/icebreaker: cleanup a bit.
2020-03-09 19:16:02 +01:00
4656b1b2ad
software/common: fix LTO checks.
2020-03-09 19:08:27 +01:00
2a91deadcb
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-03-09 19:03:05 +01:00
38d7f8a6e6
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
2020-03-09 19:02:23 +01:00
1e9aa64387
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
2020-03-09 19:01:16 +01:00
197bdcb026
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
2020-03-09 16:51:18 +01:00
37869e38b8
boards: add initial icebreaker platform/target from litex-boards.
2020-03-09 11:56:55 +01:00
72af1b39eb
software/bios: add Ultrascale SDRAM debug functions.
2020-03-09 10:55:31 +01:00
6480d1803e
boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:37:31 +01:00
b02c23391a
integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2.
2020-03-08 19:17:31 +01:00
e801dc0261
soc: allow creating SoC without BIOS.
...
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
2020-03-06 20:05:27 +01:00
ecca3d801d
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
2020-03-06 14:53:59 +01:00
69ffafd81d
integration/builder: generate csr maps before compiling software.
2020-03-06 14:20:32 +01:00
e2dab06386
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
...
This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
2020-03-06 14:12:58 +01:00
e124aed9a2
software/common.mak: fix LTO refactoring issue.
2020-03-05 23:42:36 +01:00
da580e31fd
Fix copyrights
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:44:10 +01:00
020bef4197
targets/nexys4ddr: fix sdcard clocker initialization
2020-03-05 09:02:29 -05:00
9249fc90cf
Merge pull request #410 from antmicro/netv2-edid
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platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:43:02 +01:00
72f63243cd
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:27:47 +01:00
ad11ff39ad
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 11:19:29 +01:00
3770195048
bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes.
2020-03-04 18:33:08 +01:00
4c83c975b1
doc: align to improve readability.
2020-03-04 16:46:56 +01:00
4f935714de
soc/doc: remove soc.get_csr_regions support.
...
Now that SoC documentation is integrated in LiteX, this is no longer needed.
2020-03-04 16:27:11 +01:00
6893222cf1
bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help.
2020-03-04 15:53:18 +01:00
0b923aa497
build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.
...
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.
This also removes distutils dependency.
2020-03-04 09:13:26 +01:00
1d7c6943af
software/common: add LTO enable flag and cleanup.
2020-03-04 08:11:21 +01:00
b29f443fe5
litex_sim: fix with_uart parameter.
2020-03-03 19:04:18 +01:00
98e41e2e0d
targets/nexys4ddr: add default kwargs parameters.
2020-03-02 09:44:20 +01:00
598ad692a0
Merge branch 'master' of https://github.com/enjoy-digital/litex
2020-03-02 09:31:45 +01:00
a67e19c660
integration/soc_core: change disable parameters to no-xxyy.
2020-03-02 09:31:32 +01:00
ddb264f3fd
Merge pull request #405 from sajattack/sifive-triple
...
add riscv-sifive-elf triple
2020-03-02 09:30:05 +01:00
156a85b15b
integration/soc: add auto_int type and use it on all int parameters.
...
Allow passing parameters as int or hex values.
2020-03-02 09:08:30 +01:00
7e96c911b9
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
2020-03-02 09:01:05 +01:00
cb0371b330
integration/soc: add ethphy CSR in target.
2020-03-02 08:42:59 +01:00
f27225c2de
targets/nexys4ddr: use soc.add_ethernet method.
2020-03-01 21:21:01 +01:00
9735bd5bf2
integration/soc: add add_ethernet method.
2020-03-01 20:50:13 +01:00
1c74143a39
integration/soc: mode litedram imports to add_sdram, remove some separators.
2020-03-01 18:58:55 +01:00
68c013d13f
add riscv-sifive-elf triple
2020-03-01 01:39:03 -08:00
59e99bfbcd
soc/uart: add configurable UART FIFO depth.
2020-02-28 22:34:11 +01:00
9199306a65
cores/uart: cleanup
2020-02-28 22:12:05 +01:00
ea8563339f
soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
2020-02-28 22:03:40 +01:00
12a7528667
interconnect/stream/SyncFIFO: allow depth down to 0.
2020-02-28 21:54:02 +01:00
9e31bf357e
interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.
2020-02-28 16:33:18 +01:00
1e0e96f9a0
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
2020-02-28 16:25:09 +01:00
6be7e9c33d
interconnect/axi: set default data_width/address_width to 32-bit.
2020-02-28 13:20:01 +01:00
8e1d528663
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:48:48 +01:00
a7c5dd5d3e
cores/gpio: use separate TSTriple for each bit.
...
This fixes per bit OE control.
2020-02-28 09:10:28 +01:00
400492e234
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.
2020-02-28 08:32:29 +01:00
c4fd6a7f2f
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 13:00:35 +01:00
78a3223573
software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling.
...
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:
Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00
After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10
2020-02-27 12:26:27 +01:00
eab5161d47
boards: keep in sync with LiteX-boards
2020-02-27 11:18:14 +01:00
935e4effd2
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
2020-02-26 15:13:29 +01:00
d324c54eee
integration/soc: -x on soc.py
2020-02-26 14:43:01 +01:00
ee27a9e534
soc/cores/bitbang: fix missing self.comb on miso.
2020-02-25 15:57:14 +01:00
a2d6986910
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins
...
tools: litex_gen: fix missing UART pins
2020-02-25 15:53:13 +01:00
e2aebb427e
software: disable LTO with LM32 (not supported by old GCC versions easily available).
2020-02-25 15:32:36 +01:00
75b000a32f
tools: litex_gen: fix missing UART pins
2020-02-25 14:24:29 +01:00
718a65c3c9
software: enable link time optimization (LTO)
...
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
2020-02-24 16:12:21 +01:00
7a87d4e262
Fix ECP5PLL VCO frequency range
...
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
2020-02-24 14:39:59 +01:00
0c7e0bf025
integration/soc: improve presentation of SoCLocHandler's locations.
2020-02-24 13:37:38 +01:00
0042a02807
interconnect/axi: remove bus_name on connect_to_pads
2020-02-24 13:24:32 +01:00
5aba1fe824
tools/litex_gen: add bus parameter and AXI (Lite) support.
2020-02-24 12:49:42 +01:00
a3584147a5
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:52 +01:00
d86db6f12b
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:20 +01:00
18c57a64a3
tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.
2020-02-24 10:25:18 +01:00
0083e0978b
Merge pull request #396 from antmicro/external-wb
...
Add a script that allows to generate standalone cores
2020-02-24 10:01:16 +01:00
173117ad4b
Add 'volatile' qualifier to new CSR accessors
...
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.
Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.
No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
2020-02-21 14:10:13 -05:00
9e2aede8a8
tools: add script for extracting wishbone cores
2020-02-21 16:33:26 +01:00
79a14001b0
axi: add to_pads method
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-02-21 12:22:18 +01:00
e0bcb57d3d
wishbone: add extracting module signals to the top
2020-02-21 11:20:32 +01:00
53ee9a5e05
cpu/blackparrot: first cleanup pass
2020-02-20 18:50:13 +01:00
f3829cf081
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
2020-02-20 16:16:36 +01:00
3a6f97fff3
build/sim: add Verilator FST tracing support.
2020-02-20 13:53:31 +01:00
516cf40506
targets/nexys4ddr: add optional sdcard support
...
Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
d4d2b7f7c6
bios: add litesdcard test routines to boot menu
...
This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
7a2e33b817
targets/nexys4ddr: add ethernet via method instead of inheritance
...
Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
774a55a2aa
soc_core: fix missing init on main_ram
2020-02-19 14:59:58 +01:00
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets
...
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 17:54:13 +01:00
00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
659c244a0b
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 13:38:09 +01:00
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00
854e7cc908
integration/soc: improve Region logger
2020-02-18 08:27:59 +01:00
9cb8f68e82
bios/boot: update and fix flashboot, improve verbosity
2020-02-17 19:21:54 +01:00
6ed0f445b6
soc: increase supporteds address_width/paging
2020-02-17 08:36:40 +01:00
5b3808cb81
soc_core: expose CSR paging
2020-02-17 08:34:10 +01:00
0497f3ca71
soc/csr_bus: improve CSR paging genericity
2020-02-17 08:28:56 +01:00
351896bf57
tools/litex_sim: use new sdram verbosity parameter
2020-02-16 16:09:06 +01:00
67e8a042f8
integration/soc: add configurable CSR Paging
2020-02-16 12:32:05 +01:00
6576470179
soc_core: add back identifier
2020-02-15 19:04:47 +01:00
8f6114d0cd
Merge pull request #387 from BracketMaster/master
...
litex_sim now working on MacOS and Linux
2020-02-15 17:05:50 +01:00
3da204edd6
update to work with mac
2020-02-15 10:37:39 -05:00
3574b90924
tools/litex_sim: specify default local/remote-ip addresses.
2020-02-15 14:04:44 +01:00
aebaea7764
tools/litex_sim: add ethernet local/remote-ip arguments.
2020-02-15 14:01:56 +01:00
18a9d4ff2f
interconnect/stream: cleanup imports/idents
2020-02-14 08:08:19 +01:00
eff85a99bb
tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 14:45:15 +01:00
e4712ff7f3
soc_core: fix cpu_variant renaming regression
2020-02-13 08:34:39 +01:00
baa29f1b03
doc: fix regression with new irq manager
...
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts. This has been subsumed
into a more general `irq` object that manages the interrupts.
Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.
This fixes #385 .
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:32:44 +08:00
1620f9c5b0
soc/CSR: show alignment in report and add info when updating.
2020-02-12 21:55:30 +01:00
5b34f4cd34
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
2020-02-12 21:25:52 +01:00
2f69f607e3
integration/soc: fix refactoring issues
2020-02-12 18:16:38 +01:00
1d6ce66bf7
soc/integration/builder: update copyright, align arguments
2020-02-12 16:43:11 +01:00
b56545791c
Unify output directory handling in builder
2020-02-12 15:47:16 +01:00
e9c665a539
soc_core/soc_sdram: add disclaimer
2020-02-11 18:28:05 +01:00
5558865cbf
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
2020-02-11 18:21:41 +01:00
1b5caf56fb
soc: fix busword typo
2020-02-11 17:57:05 +01:00
8b5cc34553
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:44:24 +01:00
240a55bace
Merge branch 'master' into new_soc
2020-02-11 17:22:06 +01:00
d5ad1d56f2
soc/integration: move mem_decoder to soc_core
2020-02-11 17:19:22 +01:00
0a737cb624
soc/integration/common: simplify get_version
2020-02-11 17:16:24 +01:00
399b65fa17
soc/add_uart: fix bridge
2020-02-11 16:55:37 +01:00
160c55d1d4
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
2020-02-11 16:44:25 +01:00
b2c66b1efd
soc: avoid double definition of main_ram
2020-02-11 16:39:37 +01:00
5f9946085b
soc: improve log colors on error reporting
2020-02-11 16:24:57 +01:00
b22d2ca02b
soc: add linker regions management
2020-02-11 15:28:02 +01:00
abc31a92c6
soc: improve log presentation/colors
2020-02-11 14:50:16 +01:00
91e2797bb4
soc: fix cpu_reset_address
2020-02-11 14:17:32 +01:00
0d7430fc69
tools/litex_sim_new: remove
2020-02-11 14:05:01 +01:00
21d38701df
soc: fix build_time format
2020-02-11 13:23:53 +01:00
4d761e1afd
cores/cpu: remove separators on io_regions (requires python 3.6)
2020-02-11 13:12:54 +01:00
b43d830fda
soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices)
2020-02-11 09:30:45 +01:00
ea8e745ac2
soc_core/common: move old mem_decoder to soc_core, simplify get_version
2020-02-11 08:44:23 +01:00
e301df7f56
Allow all memory regions to be used as IO with CPUNone
2020-02-10 19:56:36 +01:00
16d1972bf8
integration/common: fix mem_decoder (shadow base has been deprecated)
2020-02-10 19:40:56 +01:00
5e11e8391f
tools/litex_sim_new: switch to dynamically allocated ethmac origin
2020-02-10 19:37:53 +01:00
dd0c71d7a1
soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin
2020-02-10 19:34:18 +01:00
e8e4537e14
soc/add_sdram: avoid L2 cache when l2_cache_size == 0.
2020-02-10 19:02:44 +01:00
dcbdb73231
soc: remove unneeded \n
2020-02-10 18:38:59 +01:00
0f1811fb51
tools/litex_sim_new: use new bus/csr/irq methods
2020-02-10 18:21:41 +01:00
d320be8ecb
soc: use io_regions for alloc_region
2020-02-10 18:19:35 +01:00
9ac09ddde5
tools: add litex_sim_new based on SoCCore and using add_sdram method
2020-02-10 18:00:46 +01:00
cbcd953dd7
soc_core: use add_rom
2020-02-10 17:43:29 +01:00
487ac3da9a
soc/add_cpu: simplify CPUNone integration
2020-02-10 17:40:46 +01:00
f7d4648ca1
soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus
2020-02-10 17:17:31 +01:00
379d47a843
soc/add_sdram: add sdram csr
2020-02-10 17:02:20 +01:00
3921b6345c
soc/add_sdram: fix rocket, shorten comments
2020-02-10 16:55:15 +01:00
14b627b466
soc/add_sdram: improve API
2020-02-10 16:38:20 +01:00
1faefdc0fa
soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
2020-02-10 16:28:11 +01:00
11dbe19084
soc_core/sdram: cleanup, add disclaimer
2020-02-10 16:21:21 +01:00
5eb88cd904
soc: add add_sdram
2020-02-10 16:01:19 +01:00
39011593ac
soc: add csr_regions, update copyright
2020-02-10 15:11:37 +01:00
d2b069516a
soc: add cpu rom/sram check
2020-02-10 14:48:46 +01:00
de100fddf5
soc: add SOCIORegion and manage it
2020-02-10 14:36:53 +01:00
6b8c425f9b
soc: reorder main components/peripherals
2020-02-10 13:07:09 +01:00
84b5df7871
soc: add add_cpu method
2020-02-09 21:56:32 +01:00
7ee9ce38a7
.gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules)
2020-02-09 19:53:04 +01:00
b676a559fd
soc: fix unit-tests
2020-02-09 19:01:03 +01:00
0a5883901a
soc: integrate constants/build
2020-02-08 22:08:37 +01:00
014d5a56a8
soc: show sorted regions (by origin) / locs
2020-02-08 21:34:26 +01:00
c69b6b7c12
soc: simplify color theme
2020-02-08 21:30:34 +01:00
1dced8183e
Merge pull request #278 from scanakci/blackparrot_litex
...
Blackparrot litex
2020-02-08 10:30:55 +01:00
3cb90297ac
soc: add add_uart method
2020-02-08 10:19:18 +01:00
e5cacb8bbd
soc_core: cleanup imports
2020-02-07 23:16:29 +01:00
33d498b826
soc_core: get_csr_address no longer used
2020-02-07 23:11:08 +01:00
1feff1d7d5
soc: integrate CSR master/interconnect/collection and IRQ collection
2020-02-07 19:50:35 +01:00
3ba7c29ed9
soc: add add_constant/add_config methods
2020-02-07 19:09:54 +01:00
29bbe4c02a
soc: add add_csr_bridge method
2020-02-07 18:49:20 +01:00
b84c291c34
soc: add add_controller/add_identifier/add_timer methods
2020-02-07 18:31:50 +01:00
9445c33e9d
soc: add add_ram/add_rom methods
2020-02-07 16:06:32 +01:00
e5a8ac1dab
soc: add automatic bus data width convertion to add_master/add_slave
2020-02-07 15:31:59 +01:00
8f67f1157d
soc/soc_core: cleanup, remove some unused attributes
2020-02-07 15:19:02 +01:00
2c6e5066a7
soc: move SoCController from soc_core to soc
2020-02-07 14:52:53 +01:00
848fa20d1e
soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler
2020-02-07 13:25:54 +01:00
39458c92eb
soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined
2020-02-06 19:50:44 +01:00
1eff0799a4
soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined
2020-02-06 18:50:17 +01:00
8bc420679a
soc/integration: initial adaptation to new SoC class
2020-02-06 18:21:13 +01:00
1d70ef6958
soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
2020-02-06 17:58:01 +01:00
62f3537db0
soc/cores: rename spiopi to spi_opi
2020-02-06 17:08:00 +01:00
f58e8188b7
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
2020-02-06 17:00:04 +01:00
c2c80b5d0a
Merge pull request #378 from betrusted-io/merge_ip
...
Request to merge I2S and SPIOPI cores
2020-02-06 16:29:33 +01:00
98e46c2708
reduce indents
2020-02-06 21:55:44 +08:00
6baa07a69b
soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC
2020-02-06 11:06:41 +01:00
d2b394a9be
update doc comments on events for i2s
2020-02-06 17:58:02 +08:00
416afd3109
add doc comment for event
2020-02-06 17:56:21 +08:00
33d9e45a8b
fix formatting on spiopi
...
Pycharm really butchered the code when I did a copy-and-paste...
it has questionable default formatting preferences.
2020-02-06 17:54:26 +08:00
9b11e9192d
cpu/vexriscv: update submodule
2020-02-06 10:50:35 +01:00
cc6ed667df
Request to merge I2S and SPIOPI cores
2020-02-06 17:25:00 +08:00
5ff02e23a0
Merge pull request #375 from xobs/add-lxsocdoc
...
Add lxsocdoc
2020-02-05 10:15:21 +01:00
1944d8d9d0
bios/main: add LiteX tagline
2020-02-04 19:14:23 +01:00
90fe585003
build/sim: allow to use environment's {C,LD}FLAGS
...
There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
2020-02-04 17:31:31 +01:00
58598d4fda
integration: svd: move svd generation to `export`
...
It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h. This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 23:49:08 +08:00
73ed7e564c
soc: doc: use sphinx toctree as it was intended
...
The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely. This patch causes it to be used correctly,
which removes the need for double-including various sections.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:34:10 +08:00
7c3bc0b09f
litex-doc: initial merge of lxsocdoc
...
lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.
This merges the existing lxsocdoc distribution into the `soc/doc` directory.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:14:41 +08:00
f3b068e2ee
tools/litex_sim: use l2_reverse flag
2020-02-03 12:03:57 +01:00
3350d33f9c
wishbone/Cache: add reverse parameter
2020-01-31 19:31:33 +01:00
eff9caee6a
soc_sdram: add l2_reverse parameter
2020-01-31 19:18:07 +01:00
de88ed282a
Fix argument descriptions
2020-01-31 18:54:25 +03:00
eb49ec217e
Pass --csr-json to the Builder
2020-01-31 18:53:50 +03:00
b69f2993e4
soc_core: add UART bridge support (simplify having to do it externally)
2020-01-31 15:12:18 +01:00
7a6c04db9e
build/altera/quartus: fix fmt_r typo
2020-01-30 13:55:13 +01:00
c6b9676db8
cpu/minerva: update (use new nMigen API)
2020-01-30 13:42:02 +01:00
9d2894727e
inteconnect/stream: use PipeValid implementation for Buffer
2020-01-30 09:36:04 +01:00
1c88c0f896
inteconnect/stream: cleanup
2020-01-30 09:32:04 +01:00
cafd9c358a
Merge pull request #366 from gsomlo/gls-csr-followup
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software, integration/export: (re-)expose CSR subregister accessors
2020-01-30 08:18:12 +01:00
ff2775c264
software, integration/export: (re-)expose CSR subregister accessors
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Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.
This restores downstream ability to override CSR handling at the
subregister accessor level.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-29 14:29:24 -05:00
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
b22ad1acfb
build/xilinx/vivado: improve readability of generated tcl/xdc files
2020-01-29 16:27:18 +01:00
7bc34a9bc7
integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).
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When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
2020-01-29 08:31:41 +01:00
c02dd5e8f9
tools/litex_sim: add ddr4 PhySettings
2020-01-28 14:28:24 +01:00
0820adbda1
tools/litex_sim: add --sdram-init parameter
2020-01-27 21:30:13 +01:00
01ae10b803
software/bios: revert M-Labs MiSoC copyright.
2020-01-27 13:12:37 +01:00
ea5ef8c1be
README: update copyright year and make sure LICENSE/README both mention MiSoC
2020-01-27 12:15:11 +01:00
95cfa6a82c
platforms/netv2: add pcie pins
2020-01-27 08:25:57 +01:00
1f43906236
soc/software/bios/sdram: ECP5 move strobe dly_sel
2020-01-26 09:55:38 +10:30
f84f57d651
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
2020-01-25 13:11:39 +10:30
52765488b5
tools/litex_sim: update copyrights and cosmetic changes
2020-01-24 13:58:49 +01:00
b280bb2ff2
Merge pull request #358 from antmicro/litex_sim_ddr
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tools/litex_sim: add support for other sdram types
2020-01-24 13:33:03 +01:00
9aa97c2e0c
tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3)
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Right now litex_sim supports only SDR memories because it uses hardcoded
PhySettings. With this change PhySettings will be generated based on
selected sdram type which will allow us to use all the different types
of sdram chips in simulation.
2020-01-24 12:30:35 +01:00
19ef19ce0d
cores/clock/create_clkout: rename clk_ce to ce, improve error reporting
2020-01-24 09:10:31 +01:00
7e08836062
Merge pull request #357 from betrusted-io/add_clk_ce
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Add clk ce
2020-01-24 09:01:57 +01:00
1f7549b4c0
add BUFIO to clockgen buffer options
2020-01-24 15:01:13 +08:00
b3f9aa11be
add option for BUFGCE to the clock generator buffer types
2020-01-24 14:58:51 +08:00
cbc081c43d
tools/litex_sim: review/cleanup sdram-module/sdram-data-width features.
2020-01-23 15:42:47 +01:00
b35ea459e7
Merge pull request #354 from antmicro/litex_sim_ddr
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tools/litex_sim: specify dram chip and data width via commandline
2020-01-23 15:34:53 +01:00
674cfcde7d
tools/litex_sim: specify dram chip and data width via commandline
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litex_sim used a single predefined DRAM chip, with this it is now
possible to specify which one to use with --sdram-module and also
its data bus width can be set using --sdram-data-width
2020-01-23 14:41:37 +01:00
b23f13d960
Merge pull request #351 from antmicro/fix_sram_size_argument
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Fix sram size argument
2020-01-23 14:16:02 +01:00
7a05353aa7
soc_core: rename integrated_sram_size argument
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To keep a consistent naming scheme across all arguments.
2020-01-23 13:46:09 +01:00
c4bb4169f1
soc_core: fix integrated_sram_size argument type
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Right now it's kept as a string and crashes
when trying to do math operations on it.
2020-01-23 13:45:16 +01:00
5845df76cc
build/xilinx/vivado: add pre_placement/pre_routing commands
2020-01-21 19:00:58 +01:00
1388088240
cores/icap: add add_timing_constraints method
2020-01-21 14:08:36 +01:00
2074a86ee3
cores/dna: cleanup and add add_timing_constraints method
2020-01-21 14:08:17 +01:00
d39dc8cf5d
tools/litex_sim: cleanup/simplify
2020-01-20 21:22:41 +01:00
a0d95766ac
build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80)
2020-01-20 12:55:38 +01:00
80c3dc41d3
targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation)
2020-01-20 12:10:00 +01:00
53bc18cc3f
soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions
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With add_memory_region, user needs to provide the memory origin, which should not be needed since
could be retrieved from mem_map and prevent automatic allocation which is already possible for csr
and interrupts.
New add_mem_region method now allows both: defining the memory origin in mem_map (which will then
be used) or let the SoC builder automatically find and allocate a memory region.
2020-01-20 12:05:08 +01:00
eae0e00496
cores/clock/xadc: ease DRP timings
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Hard IP blocks are fixed in location, so long/deep combinational paths routing to multiple hard IP blocks can lead to timing closure problems.
XADC and MMCM DRPs currently have their DEN pins triggered by the ".re" output of a CSR. This is asynchronously derived from a fairly complicated set of logic that involves a logic path that goes all the way back through the cache and arbitration mechanisms of the wishbone bus. On more complex designs, this is leading to a failure of timing closure for these paths, because the hard IP blocks can be located in disparate portions of the chip which "pulls" the logic cluster in opposite directions in an attempt to absorb the routing delays to these IP blocks, leading to non-optimal placement for everything else and thus timing closure problems.
This pull request proposes that we add a pipeline delay on these critical paths. This delays the commit of the data to the DRP by one cycle, but greatly relieves timing because the pipeline register can be placed close to the cluster of logic that computes addresses, caching, and arbitration, allowing for the routing slack to the hard IP blocks to be absorbed by the path between the pipe register and the hard IP block.
In general, this shouldn't be a problem because the algorithm to program the DRP is to hit the write or read CSR, and then poll the drdy bit until it is asserted (so the process is already pretty slow). The MMCM in particular should have almost no impact, because MMCM updates are infrequent and the subsequent lock time of the MMCM is pretty long. The XADC is potentially more problematic because it can produce data at up to 1MSPS; but if sysclk is around 100MHz, adding 10ns to the read latency is relatively small compared to the theoretical maximum data rate of one every 1,000ns.
Note that the xadc patch requires introducing a bit of logic into the non-DRP path. This is because without explicitly putting an "if" statement around the logic, you fall back to the non-blocking semantics of the verilog operator, which ultimately leads to a pretty hefty combinational path. By having a default "if" that should get optimized out when DRP is not enabled, when the DRP path /is/ enabled the synthesizer knows it can safely push the async signal into a simple mux as opposed to worrying about enforcing the non-blocking operator semantics to get the desired result.
2020-01-19 20:57:14 +01:00
008a089471
targets/nexys4ddr: fix typo
2020-01-17 13:17:08 +01:00
36e5274a2b
SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map)
2020-01-17 12:45:23 +01:00
46c1c5c16f
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:27:21 +01:00
5913c91caa
SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user
2020-01-17 12:16:08 +01:00
1c465f89b6
build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file
2020-01-17 10:17:19 +01:00
b4ba2a47ef
soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover
2020-01-17 06:32:00 +01:00
d15c911cac
BlackParrot initial commit
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w/ Litex BIOS simulation including LiteDRAM
w/ Litex BIOS working on FPGA excluding LiteDRAM
2020-01-16 19:13:02 -05:00
5aa516cb8d
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
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When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
2020-01-16 19:45:41 +01:00
862e784eae
cpu/vexriscv: use 32-bit signal for externalResetVector
2020-01-16 16:20:25 +01:00
f2a1673f46
targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection
2020-01-16 13:17:33 +01:00
Florent Kermarrec
kessam
Piotr Binkowski
Ilya Epifanov
Gabriel Somlo
bunnie
Feliks
rob-ng15
Piotr Esden-Tempski
Sean Cross
Karol Gugala
Paul Sajna
Jan Kowalewski
Tim 'mithro' Ansell
Xiretza
Mateusz Holenko
Yehowshua Immanuel
Mariusz Glebocki
Vadim Kaushan
Greg Davill
sadullah